Short Bio:
I am a third-year graduate student in the
ECE department at Rice University. I received my M.S. from the Zhejiang University in China. I
currently work under Dr. Joseph
R. Cavallaro in the VLSI
Signal Processing research group. I am also a member of Center for Multimedia Communication (CMC).
My current research focuses on the physical
layer design for next generation wireless communications (B3G/4G). My most
recently research focuses on VLSI architecture design for low-density
parity-check (LDPC) codes, turbo codes, convolutional codes, MIMO detection, and deep submicron digital VLSI design using Synopsys, Cadence and Mentor
tools.
Research interests:
- VLSI Signal Processing.
- Base-band wireless transmitter and receiver
design, especially MIMO transceiver.
-
ASIC/FPGA implementation for wireless
communication.
- Micro-processor design.
-
Video and Graphics accelerator design.
Projects:
- Parallel hardware design for MIMO OFDM systems –
physical layer.
- Low Density Parity Check (LDPC) encoder/decoder
architecture design
for next generation wireless communications.
-
Turbo Decoder architecture
design for 3GPP LTE/WiMax.
-
Viterbi Decoder
architecture design for wireless communications.
-
WARP:
Wireless Open-Access Research Platform
Publication:
-
Y. Sun
and J. R. Cavallaro, “A New MIMO Detector Architecture Based on a
Forward-Backward Trellis Algorithm”. in IEEE 42nd Asilomar
Conference on Signals, Systems and Computers (ASILOMAR'08). Oct. 2008,
Pacific Grove, California, USA.
(Accepted)
-
Y. Sun
and J. R. Cavallaro, “Unified Decoder Architecture for LDPC/TURBO Codes”. in
IEEE Workshop on Signal Processing Systems (SIPS'08). Oct. 2008, Washington,
D.C., USA.
(Accepted)
-
Y. Sun
and J. R. Cavallaro, “A Low Power 1-Gbps Reconfigurable LDPC Decoder Design
for Multiple 4G Wireless Standards”. in IEEE International System-on-Chip
(SoC) Conference (SOCC'08). Sept. 2008, Newport Beach, USA.
(Accepted)
-
Y. Sun,
Y. Zhu, M. Goel and J. R. Cavallaro, “Configurable and Scalable High
Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards”.
in IEEE International Conference on Application-specific
System, Architectures and Processors (ASAP'08). July 2008, Leuven,
Belgium.
-
Y. Sun, M. Karkooti and J. R. Cavallaro, “VLSI
Decoder Architecture for High Throughput, Variable Block-Size and
Multi-Rate LDPC Codes”. in IEEE International Symposium on
Circuits and Systems (ISCAS'07). May 2007, New Orleans, USA.
[PDF]
-
Y. Sun, M. Karkooti and J. R. Cavallaro, “High
Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM
Systems”. in IEEE Dallas Circuits and Systems Workshop
(DCAS'06). Oct 2006,
Dallas, USA.
[PDF]
-
M. Goel, J-F
Ren, Y. Zhu, S-J Lee and Y. Sun, “Forward Error
Correction Decoding for WiMAX and 3GPP LTE Modems”. in IEEE 42nd
Asilomar Conference on Signals, Systems and Computers (ASILOMAR'08). Oct. 2008,
Pacific Grove, California, USA. (Invited paper)
-
K. Amiri, Y. Sun, P. Murphy, C.
Hunter, J. R. Cavallaro and A. Sabharwal, “WARP, a Modular Testbed for
Configurable Wireless Network Research at Rice”, in IEEE Symposium for
Space Applications of Wireless & RFID, 2007, Houston, USA.
[PDF]
-
K. Amiri, Y. Sun, P. Murphy, C.
Hunter, J. R. Cavallaro and A. Sabharwal, “WARP, a Unified Wireless Network Testbed for Education and Research”, in
IEEE International Conference on Microelectronics Systems Education
(MSE'07), 2007, San Diego, USA.
[PDF]
Poster:
Work Experience:
