Digital VLSI CAD for Digital IC Design

Synopsys, Cadence and Mentor Design Tools for 65nm, 90nm, and 130nm IC Design

Directed by Dr. Joseph Cavallaro, the VLSI Signal Processing for Communications Group is presently involved in a number of projects to improve the real-time performance of parallel algorithms for wireless communication systems.

We have state of art IC Design tools setup at Rice University. If you have any questions regarding to the design tools, please contact us at:

Falculty Contact:
          Dr. Joseph Cavallaro
          Email: cavallar@rice.edu

Student Contact:
          Yang Sun
          Email: ysun@rice.edu
 

Synopsys Design Tools:

Installed packages:
1. Design Compiler
2. Module Compiler
3. Physical Compiler
4. Astro P&R

Locations:
[hoss]/net/dundret1/synopsys

Cadence Design Tools:

Installed packages:
1. SoC Encounter RTL-to-GDSII
2. LDV Verilog/VHDL/SystemC simulator

Locations:
[adam]/net/dundret1/cadence

Mentor Design Tools:

Installed packages:
1. Modelsim SE Plus v6.1b
2. LeonardoSpectrum 2005a
3. IC Flow v2005.1
4. Calibre v2005.3_6
5. DFT v8.2005_4
6. Analog/Mixed Signal v2005.2 (Include Mach, Eldo and AMS)
7. SST Velocity v3.4_1.2
8. ADK v3.0

Locations:
[hoss]/net/dundret1/mentor

Setup:
Bash shell user: please source /net/dundret1/mentor/mentor.setup
C shell user: please source /net/dundret1/mentor/mentor.setup.csh

Insecta Tools:

Installed packages:
1. Insecta rel 19

Locations:
[hoss]/home/ys4937/work/insecta/insecta19_rel

ASIC front-end standard cell libraries

Installed packages:
1. TSMC 0.13um 1.2V general purpose low VT
2. Chartered  0.13 um 1.2V CH130NNVT fast silicon SC
3. Chartered 0.13 um Dual-Port RAM, Single-Port RAM and ROM Compiler
4. TSMC 65nm and 90nm, TBA

Locations:
[hoss]/net/dundret1/cad/tsmc/front-end/tsmc_013_glvt
[hoss]/net/dundret1/cad/chrt_013