VLSI Design (Elec 422) - Fall 1997

Organization

Course Contents

• Overview of combinational Logic and minimization
• Sequential logic and Finite State Machines
• Overview of semiconductor physics
• PMOS and NMOS transistors
• CMOS fabrication technology (crystal growth, wafers, lithography, masks, doping, etc.)
• Layout, design rules, stick diagrams
• The latch-up effect, prevention, well contacts
• Common structures (gates, compound gates, latches, shifters, PLA's)
• Clocking strategies, 2-phase non-overlapping clock, Karplus methodology
• Design Process - hierarchical design (regularity, modularity, locality)
• Design verification tools (simulators, netlist comparators, DRC checkers, etc.)
• MOS equations, second-order effects.
• Biasing, AC and DC characteristics, load lines
• Circuit parameters, parameter extraction
• Timing, power, and size tradeoffs
• Other CMOS structures: dynamic CMOS, pseudo NMOS, BiCMOS
• Memory systems, RAM cells, ROMs, DRAM cell structures
• Address line drivers, bit sensors in DRAMs
• Timing, power, and technology issues in memory design

Required Textbooks

1. Weste & Eshraghian ``Principles of CMOS VLSI Design'' Second Edition, Addison-Wesley, 1994.
2. VLSI Design I Packet (Available at Rice Campus Store Textbook Service Counter)

Supplementary Reading

1. Mead and Conway, Introduction to VLSI Systems, Addison-Wesley
2. Peterson and Hill, Introduction to Switching Theory and Logical Design, John Wiley
3. B. Streetman, Solid State Electronic Devices
4. Sze, VLSI Technology, McGraw-Hill

Other Useful Information

1. Students are required to enroll in Elec423 (VLSI Design II) during Spring 1997. This is due to contractual obligations with the MOSIS fabrication service, to provide a report on the success of the fabricated chip.
2. The chip fabrication project is a group effort. Students will work on the project in groups of three. However, each individual must have well-defined responsibilities within the group, to be reflected in the final project report.
3. The project is the defining core of this course. Short term goals and deadlines specified in handouts are intended to help you in project time management. Meeting these individual short term deadlines is mandatory.
4. Homeworks are designed to help assimilate the material and also to prepare the students for the design process in your project. Homeworks are not pledged, and students are encouraged to discuss the problems. They may help one another through a discussion of methods and approaches to solving the problems. However, the submitted homework must be entirely the student's own product, in the sense that it should not, even in part, contain exact copies of (whole or part of) solutions from other students, or from previous year(s), or text, graphs, plots, tables, data and/or computer files taken from any source.
5. Handouts and on-line examples are provided to assist in learning the software tools needed for the homeworks (and project).
6. Late homeworks will not be accepted. Final design of the chip is due Tuesday December 10, and cannot be extended. Final project report is due later in the examination period.
7. The midterm exam will be on Tuesday November 19.
8. Office hours are Tuesdays and Thursdays, 4:00-5:00pm, Abercrombie A224. You can also come see me with an appointment.

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