Project Description

We are building an ALU. The ALU will have 2 input registers, an instructions register (4 bits) and also output register (8 bits). The input bus will be 8 bits wide and will be used for the loading of registers 1 and 2 from either outside input or from register 3. There will be two internal busses (will call them buss i1 and buss i2) carrying the information from registers 1 and 2 to the operator module.

Add, And, Or operands will use both input registers one and two. All the other operands will use only register one since they do not require the use of seconds input.

ALU will also have 1 and -1 generators for increment and decrement -- they will be conected to internal bus i2 (because all one register operations are performed on register 1) , and will be activated when neccessary through high impedance buffers.

The operator module will contain 7 operators. The operators will all be connected to an inner "output" bus which will be connected to the output register 3. The value of the data on the bus will be controlled with high impedance buffers connected to each operator, depending on which buffer is activated that operator's output will be on the buffer. All the operators will compute all of the operations at the same time but only the desirable output will be on the bus.

All of the operations will take one clock (A) cycle to complete, thus a simple scheme will be used to decode each instruction in the PLA.

The ALU will use a 2 clock system, with clock B being offset 90 degrees from clock A. The instruction register (4bits) will be clocked with clock B, 90 degrees ahead of clock A, thus the decoding PLA will have an appropliate set of control signals ready when the input data in registers 1 and 2 will be clocked by clock A (if neccessary). The output register 3 will be clocked by clock B. ALU will have flags showing 0 output, overflow, and also flags will show lost bits during shift operations (these will be clocked with clock B).

ALU will have 7 operators in the opertor module

ADD (with increment and decrement)
NEGATE (two's compliment)
NOT (bitwise)
OR (bitwise)
AND (bitwise)
LEFT SHIFT (incoming bit either 1 or 0)
RIGHT SHIFT (incoming bit either 1 or 0)


Pins:

3 GND
3 Vdd
1 clock A
1 clock B
8 input bus
8 output bus
4 instrustion input bus
1 flag: zero ouput
1 flag: overflow
1 flag: bit that was shifted out
----
31 total

Remaining 9 bits will be used to test various internal signals.