JAWs CPU - Current Status

17 November 1998

After completing magic layout of all of our subcells, we have discovered that the ALU has a problem. The shift structure will need substrate contacts. Once the ALU is fixed, we should be finished with subcell layout. We have begun preliminary brainstorming on the overall layout of our functional blocks and are now ready to begin final assembly of the CPU.

We have performed a more thorough analysis of our timing (since our last meeting with Dr. Cavallaro). As a result, we have changed our system timing to facilitate greater robustness of the instruction fetching and latching. The logic diagram, state machine, and timing diagrams have been changed to reflect this.

We continue to work on the PLA, and are having some strange problem regarding optimization and "don't cares". This will not stop us from proceeding with assembly. Some limited optimization will still be possible, but unless we find a way to overcome the mpla limitation, we will have a partially optimized PLA.

We have also decided on a final pin allocation. It will allow us complete control of the chip, as well as a comprehensive look at key points of the circuit.

Our goal at this point is to have a working layout before Thanksgiving. This would leave us with only analysis to perform after the break. We shall see how this develops.

13 November 1998

We have completed magic layout of all subcells (including the ALU), and are ready to begin the CPU assembly.

We also performed a timing analysis for each of our instructions, ensuring that it will all work together.

We rewrote the MEG file and generated a new PLA. It is interesting to note that the PLA we generated when the MEG file contains no "don't cares" was smaller than the PLA we created when the MEG file contains "don't cares". Needless to say, we will not use the question-mark "don't cares" in our MEG file.

Some matters we need to discuss include memory access. With a 70ns (max) access time from the off-chip memory, we need to decide where to latch it. The 70ns will be a severe limitation to clock speed, possibly driving it as low as 3MHz.

27 October 1998

We have completed Magic design for all of our "building blocks". We agreed upon standards for common cells and created a library of standard logic cells to be used throughout our design. Also, as generic cells to be used in our design, we have designed our latches and multiplexers. Finally, we completed design of our Manchester adder, our register file, the program counter increment unit, and the custom logic for equal zero and greater than zero detection.

The links below refer to screen captures of the magic layout for each cell. Each cell has been verified somewhat extensively with IRSIM.

Standard Logic Cells

Our standard cells all have a height of 48 lambda. For symmetric rise/fall times, we chose to make all p-type channels 6 lambda wide, while our n-type channels remain 3 lambda wide. At the moment, the following are the only cells we feel need to be made standard, but this list is flexible.
• Inverter
• 2-input NOR
• 3-input NOR
• 4-input NOR
• 2-input NAND
• 2-input XOR: (1) Routing of m1 allowed at bottom, (2) No m1 routing at bottom

Latches

For our latch, we began with the latch designed in our homework #1, and made changes to bring it up to our standards. Click here to see our 1-bit latch. It may be extended easily to n-bits.

Multiplexers

We have designed a 1-bit multiplexer to choose between two input bits. A 2-input n-bit multiplexer will be made by stacking the 1-bit multiplexers.

Manchester Adder

For our Manchester adder (part of the ALU), we started with a one-bit add cell. Stacking 4 of these, we obtain our adder.

Register File

Our register file will consist of 4 4-bit general purpose registers. Each storage cell will be implemented as a 2 read port/1 write port SRAM cell. Decoding for the read and write lines will be performed by 3 2-to-4 decoders.

For memory access instructions, we will use one 4-bit memory access register.

Add-one Unit

To increment the PC, we add one to an 8-bit number. Our add-one unit accomplishes this. We designed a 1-bit cell for each bit of the number, intending to use top-to-bottom carry. To use alternate mirroring, however, we had to design two add cells: one to carry from Vdd to GND and one to carry from GND to Vdd. This figure shows these two units together, with alternate mirroring. To accomplish an 8-bit add, we will use 4 of these dual units.

Zero Branch Logic

For our equal zero detection, we will use the standard 4-input NOR gate.

To detect greater than zero, we created a special logic block using a 2-input NOR and a 3-input NOR.