Circuit Design

The table below contains plots of all the low level cells along with simulations.

Plots of subcells	Irsim simulation
8 bit adder	Simulation
Full adder	Simulation
8 bit AND	Simulation
8 bit OR	Simulation
8 bit NOT	Simulation
CAF	Simulation
Square Root	Simulation
Comparator	Simulation
Transmission gate	Simulation
AND	Simulation
OR	Simulation
NOT	Simulation
Latch	Simulation
Register	Simulation