Our initial idea for the project is to implement an ALU with the added functionality of a square root operation. The ALU will have an 8 bit word size and the architecture will be accumulator based. The operands will be considered as two's complement numbers for all the arithmetic operations, however, they will be considered as a ordinary binary numbers for the square root operation. Our idea for the square root operation is to use an iterative algorithm such as:
S(n) = 0.5[S(n-1) + A/S(n-1)].
S(n-1) is an initial estimate of the square root of A. S(n) approaches S(n-1) as S(n-1) approaches square root of A.All operations will execute in a single clock cycle except for the square root operation which will take a variable number of cycles depending on how quickly it converges to the square root.
This is a table of some of the operations that we plan to implement :
Mnemonic |
Operation |
| ADD A | Acc = Acc + A |
| SUB A | Acc = Acc - A |
| AND A | Acc = A && Acc |
| OR A | Acc = A || Acc |
| LOAD A | Acc = A |
| SHFTR A | Acc = Acc>>A |
| SHFTL A | Acc = Acc << A |
| SQRT A | Acc = sqrt(acc), A=initial estimate |
| NOT | Acc = !Acc |