Kartik Mohanram

ECE Assistant Professor
Rice University

Defects and Faults: Nemesis or Opportunity? Part 2

Basic extrapolations from the International Technology Roadmap for Semiconductors indicate that manufacturing defects and transient faults -- in both devices and interconnect -- will emerge as the primary showstopper to achieving increased performance and reliability in extremely scaled silicon and emerging technology alternatives.

This session will summarize these challenges and discuss some of our current research efforts across the design hierarchy at the device/interconnect level. It will include a discussion about systematic and innovative characterization of nanoscale electronic properties of single molecule devices, carbon nanotubes, and submicron interconnects, using a variety of scanning probe microscopies. The focus is on the distributional character of performance variability and how it varies with dimensionality and material composition. At higher levels of design abstraction, the session will discuss the development of suitable generic such as parameterized, device and circuit models allowing layered variability modeling, simulation, and model reduction. The discussion includes collaborative components of this research that include the development of architectures, methodologies and tools suitable for designing future computing systems based on probabilistic multiscale design.
Tuesday, September 20, 2005
3:00p.m. - Abercrombie Labs A227
Rice University
* Biography:

Kartik Mohanram received his BS in 1998 from the Indian Institute of Technology, Bombay and PhD in 2003 from the University of Texas at Austin, both in Electrical Engineering. He was a member of CATLAB (Computer-Aided Test Lab). Mohanram served on the ACM/SIGDA Programming Contest at the International Conference on Computer-Aided Design (ICCAD) -- CACAthlon 2004 organizing committee, and the organizing committee for the annual PhD Forum at the Design Automation Conference. His interests include the development of methodologies for the costeffective incorporation of concurrent error detection circuitry in integrated circuits.

ECE Affiliates Meeting - Afternoon Session



Last modified: September 26, 2005