While the design of modern computing systems cuts across disciplinary boundaries, from operating systems to physical design, a common bottleneck arises from the physical limitations and utilization efficiency of interconnects throughout the system. A current focus of the Computer Engineering group at Rice is system partitioning and interconnect modeling. At the higher levels, the interconnect fabric between processors, co-processors, memory, and peripherals impedes the flow of data. At the lower levels, aggressive process technology scaling coupled with increasing operating frequencies will exacerbate the delay, noise, and power problems that already plague today's designs. This challenge in moving data rapidly through computer systems is becoming a key barrier in all scales of systems from massive network servers down to mobile wireless handheld devices. In this talk, I will first present an overview of our multi-level interconnect research. I will then focus on the application area of wireless communication systems and algorithm mapping to parallel architectures on heterogeneous application-specific instruction set processors. Design exploration is critical to determine an efficient architecture to balance the goals of improved data rate and bit error rate performance with area and power limitation constraints.
11:30am
McMurtry Auditorium, Duncan Hall 1055
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