Peter J. Varman

pjv@ece.rice.edu

Publications

Associate Professor in Electrical and Computer Engineering
Parallel Algorithms and Architectures, Parallel I/O, Database Systems

B. Tech. (1978) Indian Institute of Technology, Kanpur
M.S.E.E. (1980) University of Texas at Austin
Ph.D. (1983) University of Texas at Austin

Professor Peter Varman's research interests are parallel algorithms and architectures, parallel I/O, and the performance of database systems. His research in parallel computing is directed towards understanding the impact of the memory hierarchy (processor caches to I/O) on the performance of parallel programs. His research deals with the design, analysis, and performance evaluation of parallel algorithms with special emphasis on non-numerical problems like sorting and searching, graph theory, and computational geometry.

One aspect of Professor Varman's work deals with identifying appropriate algorithmic paradigms that exploit the memory hierarchy in shared-memory multiprocessors and the extension of these techniques for distributed-memory systems. The second focuses on the effect of different parallel I/O organizations on performance. He uses analytic techniques and simulation studies to determine the impact of different data placement methods, buffer management algorithms, and prefetching strategies. Professor Varman collaborates closely with members of IBM's Data Base Technology Institute in adapting the results of basic research to their database systems.

Another of Professor Varman's current interests is the study of storage and access methods for handling large data sets arising in temporal and scientific databases. He is working on the design of efficient indexing mechanisms, data partitioning for tertiary storage, and query processing algorithms.

Professor Varman worked previously in VLSI architectures and maintains an interest in this area.

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