End-to-end performance bottlenecks are increasingly encountered at the network edges. In metropolitan backbones, such networks are most often configured as rings due to their fault tolerance properties. Today's packet rings are formed via point-to-point packet-based duplex connections of Metro Ethernet or protocols such as Resilient Packet Ring (IEEE 802.17). Our goal in this project is to devise a high-performance distributed ring scheduling and medium access algorithm which is able to ensure a traffic class fair and/or guaranteed rate access throughout the ring. We have devised a new protocol termed DVSR and developed a 1 Gb/sec network processor prototype and testbed implementation.
 

People

Faculty:
Edward W. Knightly
Steve Sheafor (adjunct)

Ph.D. Students:
Violeta Gambiroza 
Ping Yuan
Yonghe Liu

Undergraduates:
Jyoti Uppuluri
Joshua Robinson

Alumni:
Laura Balzano
Archana Krishna

Tools

  • DVSR: an enhanced fairness algorithm for packet rings

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  • RIAS: the now-standardized fairness reference model for RPR

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  • Rice Packet Ring Simulator: an ns-2 open source simulator for RPR and DVSR

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Papers

Presentations