Dr. Michael C. Brogioli is currently the Chief Architect of the StarCore DSP Compiler Framework at Freescale
Semiconductor in Austin, Texas, USA. He is also researching next generation embedded DSP core architectures for
baseband processing, and next generation SOC platform architectures for baseband processing at Freescale.
In addition to his work with Freescale Semiconductor, Dr. Brogioli is an Adjunct Professor of Electrical and
Computer Engineering at Rice University in Houston, Texas, USA. He teaches graduate level seminars on embedded
computer architectures and their relation to compiled languages. In addition, he advises senior design projects
based around intelligent, real time audio processing using Freescale's line of StarCore based multi-core platforms.

Dr. Brogioli graduated from Rice University's Department of Electrical and Computer Engineering in
2007. His Ph.D. thesis advisor is Dr. Joseph Cavallaro with committee members Dr. Keith D. Cooper and
Dr. Scott Rixner. His research interests lie in heterogeneous DSP architectures, simulation of SOC type
architectures, compiler technology for DSP architectures, and embedded computing in general. He is the
author of the Spinach Simulation Environment for network interface architectures, as well as multi-processor
DSP and FPGA based embedded architectures. He is also the author of the RISD compiler infrastructure for multi-
clustered, scalable, VLIW based DSP architectures.

He received his B.S. Cum Laude in Electrical Engineering from Rensselaer Polytechnic Institute in 1999. His
M.S. and Ph.D. were received in Computer Engineering from Rice University in 2003 and 2007 respectively.
During his graduate research, he worked with Texas Instruments' Advanced Architecture and Chip Technology
group, as well as Intel's Microprocessor Research Labs and IA-64 Compiler Group. In 2009 he founded
Brogioli Consulting LLC, providing expert witness testimonials and consulting efforts to various law firms
and technology startups on both the national and international level.