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2319 Alberton Lane |
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Rice University, MS 380 |
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Pearland, TX 77584 |
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Dept. of Electrical & Computer Engineering |
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(281) 412-0133 |
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Houston, TX 77251-1892 |
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(713) 348-4719 |
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(713) 348-6196, Fax |
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August 31, 2004 |
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Cornell University, Ph.D. in Electrical Engineering, August 1988.
Thesis Title: VLSI CORDIC Processor Architectures for the Singular Value Decomposition.
Thesis Advisor: Franklin T. Luk.
Princeton University, M.S. in Electrical Engineering, June 1982.
University of Pennsylvania, B.S. in Electrical Engineering, (magna cum laude), May 1981.
· 2002-Present Rice University, Professor,
· 1994-2002 Rice University, Associate Professor (Tenured), Electrical & Computer Engineering, (Courtesy appointment in Computer Science Department, 2000-Present).
· 1996-1997 National Science Foundation, Program Director, Systems Prototyping and Fabrication Program, MIPS Division, CISE Directorate.
· 1988-1994 Rice University, Assistant Professor, Electrical & Computer Engineering
· 1987-1988 Cornell University, IBM Graduate Fellow
· 1986-1987 Cornell University, Research Assistant
· 1983-1986 Cornell University, Teaching Assistant
· 1981-1983 AT&T Bell Laboratories, MTS, Special Business Services Laboratory
· IEEE Computer Society Distinguished Lecturer, 2004-2006
· IEEE Application-Specific Systems, Architectures and Processors Conference, Best Paper Award, (with B. Haller and J. Götze), 1997.
· IEEE Circuits and Systems Society Chapter of the Year Award, (accepted as Chair of the Houston Chapter), 1996
· Hershel M. Rich Invention Award, Rice Engineering Alumni, 1994
· IEEE Region 5 Award for service as Student Branch Counselor, 1992
· NSF Research Initiation Award, 1989-1992
· IBM Graduate Fellowship, 1987-1988
· AT&T Graduate Study Program, 1981-1982
· Member of Tau Beta Pi and Eta Kappa Nu
· National Merit Scholarship, 1977-1978
· VLSI DSP architectures and parallel algorithms for wireless communications and robotics
· VLSI systems design and microlithography
· Fault-Tolerant robotic and computer systems
· High-speed computer arithmetic
1. “MRI: Development of a National University Wireless Testbed: Rice Configurable Baseband Architecture,” NSF EIA-0321266 (PI) $374,000, 2003-2006, (with B. Aazhang, J. P. Frantz, and A. Sabharhal (Co-PIs), (with O. Takeshita, OSU, and D. Goeckel, Umass, and M. Fitz, UCLA (Collaborators).
2. “Algorithms for Next Generation High Data Rate Wireless Systems,” Nokia Corporation, (Co-PI), $586,047, 2003-2005, (with B. Aazhang (PI), A. Sabharwal (Co-PI).
3. “A Research Platform for Seamless Wireless Networks supporting Multimedia Applications,” Nokia Corporation and Texas Instruments, Inc., (PI), $555,000, 2002-2004, (with B. Aazhang (Co-PI)).
4. “CISE Research Resources: A Comprehensive Multi-tier Wireless Network Development Platform,” NSF EIA-0224458 (PI), $187,244, 2002-2004, (with J. P. Frantz (Co-PI), A. Sabharwal (Co-PI), E. Knightly (Co-PI), B. Aazhang (Co-PI)).
5. “Leadership University: New Applications of DSPs in Networking, Wireless Communications, and Image Processing,” Texas Instruments, Inc., (Co-PI), $1,000,000, 2002-2004, (with C. S. Burrus (PI), B. Aazhang (Co-PI), E. W. Knightly (Co-PI), R. G. Baraniuk (Co-PI), R. Nowak (Co-PI), and M. Orchard (Co-PI)).
6. “VLSI Systems Design Education,” AMD Corporation, (PI), $51,000, 1999-2004.
1. “Signal Processing Algorithms and Architectures for CDMA Systems,” Nokia Corporation, Helsinki, Finland, (Co-PI), $444,528, 2000-2002, (with B. Aazhang (PI)).
2. “Seamless Multi-tier Wireless Networks for Multimedia Applications,” NSF ANI-9979465, (Co-PI), $700,000, 1999-2003, (with B. Aazhang (PI), R.G. Baraniuk (Co-PI), E.W. Knightly (Co-PI), and D.S. Wallach (Co-PI)).
3. “Implementation of W-CDMA Networks: Advanced Mobile and Basestation Receiver Prototyping,” Texas TDTP, (PI), $211,148, 2000-2002, (with D.H. Johnson (co-PI)).
4. “Development of a Testbed for Wireless Multiuser Communication Systems,” Nokia Corporation and Texas Instruments, Inc., (PI), $500,781, 1998-2002 (with B. Aazhang (Co-PI)).
5. “Leadership University: New Applications of DSPs in Networking and Integrated Wireless Sensors,” Texas Instruments, Inc., (Co-PI), $1,000,000, 1999-2001, (with C. S. Burrus (PI), B. Aazhang (Co-PI), E. W. Knightly (Co-PI), and R. G. Baraniuk (Co-PI)).
6. “Development of a High Speed Wireless LAN,” Nokia Corporation, (Co-PI), $241,622, 1999-2000 (with B. Aazhang (PI), E. Erkip (Co-PI), and R.G. Baraniuk (Co-PI)).
7. “Development of Multiuser Transceivers for Wireless CDMA Communications,” Texas Technology Development and Transfer Program. TDTP 003604-044, (Co-PI), $201,336, 1998-1999, (with B. Aazhang (PI)).
8. “A Web-Based Engineering Design Tutor,” A.W. Mellon Foundation, (Co-PI), $570,000, 1998-2000, (with M. Terk (PI) and W. Zwaenepoel (Co-PI)).
9. “Development of Monitoring and Diagnostic Methods for Robots Used in Remediation of Waste Sites,” DOE DE-FG07-97ER14830, (PI), $94,944, 1997-1999, (subcontract via Foster-Miller Technologies, Inc., Latham, NY).
10. “Advanced Signal Processing for Multiuser Wireless Communications,” Texas Advanced Technology Program, TATP 003604-049, (Co-PI), $255,000, 1996-1997, (with B. Aazhang (PI)).
11. “Architectures for Multiuser Detection and Channel Estimation in CDMA Communication Systems,” NSF NCR-9506681, (Co-PI), $303,597, 1995-1999, (with B. Aazhang (PI)).
12. “Dynamic Fault Tolerance Methods for Robotics,” NSF IRI-9526363, (Co-PI), $50,000, 1995-1997, (with I. D. Walker (PI)).
13. “Architectures for Multiuser Detection and Channel Estimation in CDMA Communication Systems,” Nokia Corporation, Helsinki, Finland, (Co-PI), $511,785, 1995-1999, (with B. Aazhang (PI)).
14. “Failure Mode Analyses of the Hanford Manipulator,” DOE Westinghouse Hanford Company DE-AC04-94AL850, (Co-PI), $52,743, 1994-1995, (with I. D. Walker, (PI).
15. “Enhanced VLSI Microelectronics Manufacturability using Closed-Loop Photolithographic Simulation,” NSF Materials Synthesis and Processing Initiative DDM-9202639, (PI), $330,000, 1992-1996, (with F. K. Tittel (Co-PI) and W. L. Wilson, Jr. (Co-PI)).
16. “Dynamic Fault Reconfigurable Robotic System Architectures,” DOE Sandia National Laboratories Contract #18-4379A, (PI), $309,017, 1991-1996, (with I. D. Walker (Co-PI)).
17. “VLSI CORDIC Parallel Processor Architectures for the SVD,” NSF Research Initiation Award MIP-8909498, (PI), $69,400, 1989-1992.
1. “VLSI Architectures for Configurable Communication Systems,” NSF, (PI), (with J.P. Frantz (Co-PI)).
2. “CRI: Shared Resources to Explore Multi-level InterConnect Architectures (MICA),” NSF, (PI), (with K. Mohanram, Y. Massoud, S. Rixner (Co-PIs)).
1. “Advanced Plotting Systems for VLSI Design and Education,” Hewlett-Packard Corporation, $19,000, 2000.
2. “Parallel SVD of Arbitrary Matrices on the CM5,” Army High Performance Computing Research Center, Minneapolis, MN. Access to Connection Machine 5, 1992-1995.
3. Texas Instruments, Houston, TX. TMS320 Digital Signal Processing Hardware and Software, 1991-Present.
4. Technology Modeling Associates, Palo Alto, CA. DEPICT Photolithography Simulation Software, 1991-1995.
· Elec 422, VLSI Design I
· Elec 423, VLSI Design II
· Elec 437/630, Multi-tier Wireless Networks (team project course)
· Elec 522, Advanced VLSI Design
· Elec 525, Advanced Computer Architecture
· Elec 625, High Performance Processor Design (with J. K. Bennett)
· Elec 693, 694, Advanced Topics Seminars - Computer Systems
· Elec 490, Senior Independent Projects
· Elec 491, 492, Senior Honors Projects
· Elec 590, 599, Graduate Independent Projects
Ph.D. May 2004, “Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation”
M.S. May 2000, “Baseband Architecture Design for Future Wireless Base-Station Receivers”
Current Address: sridhar.rajagopal@wiquest.com, WiQuest, Inc., Allen, TX
Ph.D. January 2002, “Derivation and Application of Nonlinear Analytical Redundancy Techniques with Applications to Robotics” (co-supervised with I. D. Walker).
M.S. May 1997, “Fault Tolerance in Robot Systems.”
Current Address: mleuschen@nomadics.com, Nomadics, Inc., Stillwater, OK
Ph.D. September 2000, “Multiuser Information Processing in Wireless Communication”
M.S. May 1997, “Detection Algorithms for CDMA Systems.”
Current Address: sumand@bell-labs.com, Lucent, Bell Labs, Murray Hill, NJ.
Honored by MIT Technology Review in Top 100 Young Innovators of 2004
Ph.D. December 1998, “Algorithms and Architectures for Channel Estimation in Wireless CDMA Communication Systems,”
M.S. May 1995, “An Integrated CAD Framework Linking VLSI Layout Editors & Process Simulators.”
Current Address: chaitali@ti.com, Texas Instruments, Dallas, TX.
Ph.D. May 1996, “Parallel Algorithms and Architectures for Near-Far Resistant CDMA Acquisition.”
M.S. May 1991, “Architectural, Numerical and Implementation Issues in the VLSI Design of an Integrated CORDIC-SVD Processor.”
Current Address: kkota@cicada-semi.com, Cicada Semiconductor Corporation, Austin, TX.
Ph.D. May 1994, “Dynamic Fault Detection and Intelligent Fault Tolerance for Robotics,” (co-supervised with I. D. Walker)
M.S. December 1991, “Fault Detection and Fault Tolerance Methods for Robotics,” (co-supervised with I. D. Walker)
Current Address: mvisinsk@oss.oceaneering.com, Oceaneering Space Systems, Houston, TX.
Ph.D. May 1994, “Efficient VLSI Architectures for Matrix Factorizations.”
M.S. May 1991, “A Systolic VLSI Architecture for Complex SVD.”
Current Address: hemkumar@crystal.cirrus.com, Crystal Semiconductor Corp., Austin, TX.
M.S. May 2004 “Semi-Parallel Architectures For Real-time LDPC Coding”
M.S. May 2004 “Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures”
M.S. January 2003 “VITURBO: A Reconfigurable Architecture for Ubiquitous Wireless Networks”
Current Address: mani.vaya@cirrus.com, Cirrus Logic, Austin, TX.
M.S., January 2003“Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receiver.”
Current Address: vikram.chandrasekhar@ni.com, National Instruments, Austin, TX
M.S. May 2002,“Rapid Prototyping of Wireless Communications Systems”
Current Address: bryanj@clemson.edu, Clemson University, Clemson, SC.
M.S. May 2001, “A Reconfigurable Decoder Architecture for Wireless LAN and Cellular Systems”
Current Address: kanu@engim.com, Engim Inc., Acton, MA.
M.S. May 1999, “A Software Simulation Testbed for CDMA Wireless Communication Systems.”
Current Address: vishwas.sundaramurthy@nokia.com, Nokia Corporation, Irving, TX.
M.S. May 1999, “Implementation Issues of Multiuser Detection in CDMA Communication Systems.”
Current Address: gang.gary.xu@nokia.com, Nokia Corporation, Irving, TX.
Yuanbin Guo, (5th year Ph.D. student); Advanced Baseband Algorithms and Architectures for Interference Suppression in WCDMA and WLAN Systems (part-time at Nokia Research Center.),
Michael Brogioli,(5th year Ph.D. student); Reconfigurable and VLIW Style Architectures for Task Based Embedded Computing Workloads,
Marjan Karkooti(4th year Ph.D. student); Wireless Radio Testbed Architectures and LDPC Decoding,
Predrag Radosavljevic(4th year Ph.D. student); Wireless Radio Testbed Architectures and Application Specific Instruction Processors (ASIP),
Manik Gadhiok (2nd year M.S. student); VLSI System Design for ASIPS,
Frank Livingston, (4th year Ph.D. student); Power Efficient VLSI Multi-tier Network Interface Card Architectures (on leave).
Krishna Kiran Mukkavilli, Ph.D. (ECE) (Aazhang, Chair) 2003
Mohammad Jaber Borran, Ph.D. (ECE) (Aazhang) 2003
Liang Sun, Ph.D. (ECE) (Clark) 2003
Li Xu, Ph.D. (CS) (Cooper) 2003
Dinesh Rajan, Ph.D. (ECE) (Aazhang) 2002
Chu Xiang, Ph.D. (ECE) (Young) 2001
Srikrishna Bhashyam, Ph.D. (ECE) (Aazhang) 2001
Parthasarathy Ranganathan, Ph.D. (ECE) (Adve) 2000
Andrew Sendonaris, Ph.D. (ECE) (Aazhang) 1999
Yile Guo, Ph.D. (ECE) (Aazhang) 1999
Juan A. Rodriguez, Ph.D., (ECE) (Wilson) 1998
Raghavendra K. Madyastha, Ph.D., (ECE) (Aazhang) 1997
Deirdre L. Hamilton, Ph.D., (ECE) (Walker) 1996
Arati Deo, Ph.D., (ECE) (Walker) 1995
William Dawkins, Ph.D., (ECE) (Sinclair) 1993
Richard Murphey, Ph.D., (ECE) (Clark) 1991
Chris Steger, M.S., (ECE) (Aazhang, Chair) 2004
Nasir Ahmed, M.S., (ECE) (Aazhang) 2002
Mahsa Memarzadeh, M.S., (ECE) (Aazhang) 2001
Ahmad Khoshnevis, M.S., (ECE) (Aazhang) 2001
Ozgur Ertug, M.S., (ECE) (Varman) 2000
Krishna Kirin Mukavilli, M.S., (ECE) (Aazhang) 2000
Tarik Muharemovic, M.S., (ECE) (Aazhang) 2000
Damian Dobric, M.S., (ECE) (Bennett) 2000
Nadeem Ahmed, M.S., (ECE) (Baraniuk) 2000
Chu Xiang, M.S., (ECE) (Young) 1999
Dinesh Rajan, M.S., (ECE) (Aazhang) 1999
Yile Guo, M.S., (ECE) (Young) 1996
David Chung, M.S., (ECE) (Clark) 1996
Andrew Sendonaris, M.S., (ECE) (Aazhang) 1995
Michael G. McMahon, M.S., (ECE) (Clark) 1995
Stephen E. Bensley, M.S., (ECE) (Aazhang) 1994
Juan A. Rodriguez, M.S., (ECE) (Wilson) 1994
Jai Tang, M.S., (ECE) (Varman-Sinclair) 1993
Jay Greenwood, M.S., (ECE) (Bennett) 1992
Deirdre Hamilton, M.S., (ECE) (Bennett-Walker) 1992
Samir Khushalani, M.S., (ECE) (Clark) 1992
Ping Tian, M.S., (ECE) (Clark) 1992
Arati Deo, M.S., (ECE) (Walker) 1991
Vinay Pai, M.S., (ECE) (Varman) 1991
William Dawkins, M.S., (ECE) (Sinclair) 1990
· Judge, Rice Undergraduate Research Symposium, 2003.
· Faculty Contact, Undergraduate Recruiting, 2003-2003.
· Member of University Committee on Undergraduate Admissions, 1997-1999.
· Member of Faculty Council, 1991-1992.
Chair of Elections Committee
Member of Tenure and Ethics Committee.
· Engineering Divisional Advisor, Lovett Residential College, 1990-1996.
· Member of University Committee on Undergraduate Teaching, 1990-1991.
· Faculty Associate, Lovett Residential College, 1989-1999.
Outstanding Associate, 1990-1991, 1991-1992, 1992-1993, 1993-1994, 1994-1995.
· Member of Computer and Information Technology Institute, 1989-Present.
· ECE/CS Computer Systems Lab, Member, 2000-Present.
· Affiliates Committee, Chair, 1999-Present.
· Associate Director, Center for Multimedia Communications, 1999-Present.
· Member of Faculty Search Committee, 1999, 2002-2003.
· Member of Computer Committee, 1998-1999.
· Member of Graduate Committee, 1997-Present, 1988-1992.
· Chair of Computer Engineering Area Committee, 1997-1998.
· Member of Corporate Affiliates Committee, 1995-1996.
· Member of Curriculum Committee, 1994-1995.
· Member of Undergraduate Committee, 1994-1996.
· Chair of Library Committee, 1992-1994.
· IEEE Rice University Student Branch Advisor, 1990-1994.
· Chair of Safety Committee, 1990-1991.
· Member of Space Committee, 1989-1990.
· Mentor, Alliance for Graduate Education and the Professoriate (AGEP), Summer 2000.
· Faculty Mentor Program, Spring Independent School District, Spring, TX, 1990.
1999 - Present, IEEE Transactions on Robotics and Automation;
1994 - Present, Journal of VLSI Signal Processing;
1993 - Present, Journal of Computers and Electrical Engineering;
1993 - Present, Journal of Intelligent and Robotic Systems;
1993 - Present, Society for Computer Simulation Simulation Journal;
1993 - Present, IEEE Transactions on Parallel and Distributed Systems;
1993 - Present, IEEE Transactions on VLSI Systems.
1992 - Present, Journal of Robotics and Computer Integrated Manufacturing;
1992, IEEE Signal Processing Magazine;
1991 - Present, IEEE Computer Magazine;
1990, Parallel Computing Journal;
1990 - Present, Kluwer Academic Press;
1989 - Present, IEEE Transactions on Signal Processing;
1989 - Present, SIAM Journal on Matrix Analysis and Applications;
1987 - Present, Journal of Parallel and Distributed Computing;
1986 - Present, IEEE Transactions on Computers.
2002, IEEE International Symposium on Spread Spectrum Techniques and Applications; 1997, IEEE International Conference on Computer Design; 1993 - Present, International Conference on Application-Specific Array Processors; 1990 - Present, International Conference on Parallel Processing; 1989, HICSS23 - 23rd Hawaii International Conference on System Sciences; 1986 - Present, IEEE Symposia on Computer Arithmetic.
2003, Committee of Visitors, C-CR Division, CISE, National Science Foundation,
2003, Review Panelist, EIA Division, CISE, National Science Foundation,
2002, Mail Reviewer, C-CR Division, CISE, National Science Foundation,
2002, Review Panelist, C-CR Division, CISE, National Science Foundation,
2001, Site Review Panelist, EIA Division, CISE, National Science Foundation,
2000, Committee of Visitors, C-CR Division, CISE, National Science Foundation,
2000, Review Panelist, EHR Directorate, National Science Foundation,
2000, Reviewer, U.S. Civilian Research and Development Foundation,
2000, Mail Reviewer, INT Division, National Science Foundation,
1999, Review Panelist, EIA Division, CISE, National Science Foundation,
1999, Review Panelist, C-CR Division, CISE, National Science Foundation,
1998, Review Panelist, EIA Division, CISE, National Science Foundation,
1994, 1996, Review Panelist, DMII Division, ENG, National Science Foundation,
1989 - Present, Mail Reviewer, MIPS and C-CR Division, CISE, National Science Foundation.
1999-2000, Ph.D. thesis committee, Royal Institute of Technology, (KTH) Stockholm, Sweden.
1994, Ph.D. thesis committee, Indian Institute of Technology, Kharagpur.
§ Guest Editor, 2005 Special Issue on Application-specific Systems, Architectures and Processors, Journal of VLSI Signal Processing Systems, (with L. Thiele, S. Rajopadhye, and T. Noll).
§ Program Committee, 2005 IEEE International Conference on Communications (ICC), Seoul, Korea.
§ Program Committee, 2005 IEEE Microelectronics Systems Education Conf., Anaheim, CA.
§ Co-Chair, Signal Processing for Communications Symposium, 2004 IEEE Global Communications Conference (GLOBECOM), Dallas, TX.
§ General Co-Chair, 2004 IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Galveston, TX.
§ Invited Session Organizer, “VLSI Architectures and Implementations for Wireless Systems” 2004 38th Asilomar Conference on Signal, Systems, and Computers, Pacific Grove, CA.
§ Program Committee, 2004 IEEE Signal Processing Systems Conference (SIPS), Austin, TX.
§ Co-Chair, Program Committee, 2003 IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP), The Hague, The Netherlands.
§ Program Committee, 2003 IEEE Microelectronic Systems Education Conf., Anaheim, CA.
§ Chair, IEEE Computer Society Technical Committee on VLSI, 2002-2004.
§ Area Editor, Hardware and Architecture, Encyclopedia of Computer Science and Engineering, Wiley Interscience, 2002-2003 Edition.
§ Member, IEEE Transactions on VLSI, Editor-in-Chief Search Committee, 2002.
§ Program Committee, 2002 IEEE 13th International Conference on Application-specific Systems, Architectures and Processors, San Jose, CA.
§ Program Committee, 2001 IEEE Microelectronic Systems Education Conf., Las Vegas, NV.
§ Session Organizer, 2001 Texas Instruments DSP Fest, Wireless Applications, Houston, TX.
§ Session Chair, 2000 IEEE 12th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Boston, MA.
§ Session Chair, 1999 33rd Asilomar Conference on Signal, Systems, and Computers, Pacific Grove, CA.
§ Program Committee, 1999 IEEE 14th Symposium on Computer Arithmetic, Adelaide, Australia.
§ Program Committee, 1999 IEEE Microelectronic Systems Education Conference.
§ Program Committee, 1998 SPIE Symposium on Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, San Diego, CA.
§ Program Committee, 1997 IEEE International Conference on Computer Design, Austin, TX.
§ Program Committee and Publicity Chair, 1997 IEEE 13th Symposium on Computer Arithmetic, Asilomar, CA.
§ Publicity Chair, 1996 IEEE International Conference on Neural Networks, Washington, DC.
§ Guest Editor, 1995 Special Issue on Safety of Robotics Systems, Reliability Engineering and System Safety, (with I. D. Walker and K. E. Petersen).
§ Program Committee, 1995 IEEE 12th Symposium on Computer Arithmetic, Bath, UK.
§ Session Chair, 1995 IEEE 12th Symposium on Computer Arithmetic, Bath, UK.
§ Program Committee, 1994 International Symposium on Robotics and Manufacturing, Maui, HI.
§ Guest Co-Organizer, 1994 Special Issue on Fault Tolerance in Robotics, Journal of Computers and Electrical Engineering, (with I. D. Walker and M. Jamshidi).
§ Program Committee and Session Chair, 1992 SCS International Simulation Technology Conference, Clear Lake, TX.
§ Invited Session Co-Organizer, 1992 International Symposium on Robotics and Manufacturing, Sante Fe, NM, (with I. D. Walker).
§ Session Chair, 1991 SIAM Conference on Parallel Processing for Scientific Computing, Houston, TX.
§ Chair, IEEE Houston Section Circuits and Systems Society, 1990-Present.
· 2001, Hewlett Packard, Fort Collins, CO.
· 1995-, Nokia Corporation, Irving, TX and Helsinki, Finland.
· 1994, Baker & Botts, L.L.P., Patent Review, Austin, TX.
· 1990, Compaq Computer Corporation, Houston, TX.
· Association for Computing Machinery
· Institute of Electrical and Electronics Engineers
· Society for Industrial and Applied Mathematics
· Society of Photo-Optical Instrumentation Engineers
1. V. Chandrasekhar, F. Livingston, J. R. Cavallaro, Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers. International Journal of Embedded Systems, (Accepted, August 2004).
2. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Fault Residual Generation via Nonlinear Analytical Redundancy,” IEEE Transactions on Control Systems Technology, (Accepted, April 2004).
3. S. Das, E. Erkip, J. R. Cavallaro, B. Aazhang, “Low Complexity Iterative Multiuser Detection and Decoding for Real-Time Applications,” IEEE Transactions on Wireless Communications, (Revised, July 2004).
In Preparation:
4. S. Rajagopal, J. R. Cavallaro, “Truncated On-line Arithmetic with Applications to Communication Systems,” IEEE Transactions on Computers, (In preparation, August 2004).
5. S. Rajagopal, J. R. Cavallaro, S. Rixner, “Design Space Exploration for Real-Time Embedded Stream Processors,” IEEE Micro, pp. 54-66, Volume 24, No. 4, (July-August 2004).
6. B. Jones, J. R. Cavallaro, A Rapid Prototyping Environment for Wireless Communication Embedded Systems, EURASIP Journal on Applied Signal Processing, Special Issue on: Rapid Prototyping of DSP Systems, pp. 603-614, Volume 2003, No. 6, (May 2003).
7. J. R. Cavallaro, Architectures for Heterogeneous Multi-Tier Networks, Kluwer Journal on Wireless Personal Communications, pp. 285-296, Volume 22, No. 2, (August 2002).
8. S. Rajagopal, S. Bhashyam, J. R. Cavallaro, B. Aazhang, “Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers,” IEEE Transactions on Wireless Communications, pp. 468-479, Volume 1, No. 3, (July 2002).
9. S. Rajagopal, S. Bhashyam, J.R. Cavallaro, and B. Aazhang, “Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-station Receivers”, Journal of VLSI Signal Processing: special issue on ASAP, pp. 143-156, Volume 31, No. 2, (June 2002).
10. G. Xu, S. Rajagopal, J. R. Cavallaro, and B. Aazhang, “VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers”, Journal of VLSI Signal Processing: special issue on signal processing for wireless communications: algorithms, performance and architecture, pp. 21-33, Volume 30, No. 1-3, (March 2002).
11. B. Aazhang, J. R. Cavallaro, “Multi-tier Wireless Communications,” Wireless Personal Communications, Special Issue on Future Strategy for the New Millennium Wireless World, Kluwer, pp.323-330, Volume 17, (June 2001).
12. C. Sengupta, J. R. Cavallaro, B. Aazhang, “On Multipath Channel Estimation for CDMA Systems Using Multiple Sensors,” IEEE Transactions on Communications, pp. 543-553, Volume 49, No. 3, (March 2001).
13. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Evaluating the Reliability of Prototype Degradable Systems,” Reliability Engineering and System Safety, pp. 9-20, Volume 72, (2001).
14. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Subspace-based Tracking of Multipath Channel Parameters for CDMA Systems,” European Transactions on Telecommunications, pp.439-447, Volume 9, No. 5, (September - October 1998).
15. J. Feinsmith, J. H. Aylor, R. Hodson, B. Courtois, J. R. Cavallaro, J. Hines, C. Pina, M. Smith, D. Bouldin, “What’s Next for Microelectronics Education - Editorial” IEEE Design and Test of Computers, pp 95-102, Volume 14, No. 4, (October-December 1997).
16. C. Sengupta, J. R. Cavallaro, W. L. Wilson, Jr., F. K. Tittel, “Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations,” IEEE Transactions on Semiconductor Manufacturing, pp. 482-494, Volume 10, No. 4, (1997).
17. Z. L. Horvath, M. Erdélyi, G. Szabó, Zs. Bor, F. K. Tittel, J. R. Cavallaro, “Generation of Nearly Nondiffracting Bessel Beams with a Fabry-Perot Interferometer,” Journal of the Optical Society of America A, pp. 3009-3013, Volume 14, No. 11, (November 1997).
18. M. Erdélyi, Z. L. Horvath, G. Szabó, Zs. Bor, F. K. Tittel, J. R. Cavallaro, M. C. Smayling, “Generation of Diffraction-free Beams for Applications in Optical Microlithography,” Journal of Vacuum Science and Technology B, pp. 287-292, Volume 15, No. 2, (March/April 1997).
19. K. E. Petersen, I. D. Walker, J. R. Cavallaro, “Safety of Robotic Systems – Guest Editorial,” Reliability Engineering and System Safety, pp. 223-224, Volume 53, No. 3, (1996).
20. I. D. Walker, J. R. Cavallaro, “Failure Mode Analysis for a Hazardous Waste Clean-up Manipulator,” Reliability Engineering and System Safety, pp. 277-290, Volume 53, No. 3, (1996).
21. M. Erdélyi, Zs. Bor, F. K. Tittel, J. R. Cavallaro, G. Szabó, W. L. Wilson, Jr., C. Sengupta, “Enhanced Microlithography Using Combined Phase Shifting and Off-Axis Illumination,” Japanese Journal of Applied Physics, pp. L1629-L1631, Volume 34, Part 2, No. 12A, (December 1995).
22. M. Kido, G. Szabó, J. R. Cavallaro, W. L. Wilson, Jr., M. C. Smayling, F. K. Tittel, “Submicron Optical Lithography Based on a New Interferometric Phase Shifting Technique,” Japanese Journal of Applied Physics, pp. 4269-4273, Volume 34, Part 1, No. 8A, (August 1995).
23. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “A Dynamic Fault Tolerance Framework for Remote Robots,” IEEE Transactions on Robotics and Automation, pp. 477-490, Volume 11, No. 4, (1995).
24. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Robotic Fault Detection and Fault Tolerance: A Survey,” Reliability Engineering and System Safety, pp. 139-158, Volume 46, No. 2, (1994).
25. N. D. Hemkumar, J. R. Cavallaro, “Redundant and On-Line CORDIC for Unitary Transformations,” IEEE Transactions on Computers, Special Issue on Computer Arithmetic, pp. 941-954, Volume 43, No. 8, (August 1994).
26. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Expert System Framework for Fault Detection and Fault Tolerance in Robotics,” Computers and Electrical Engineering, pp. 421-435, Volume 20, No. 5, (1994).
27. I.D. Walker, J. R. Cavallaro, “Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots,” Journal of Intelligent and Robotic Systems: Theory and Applications, Special Issue on Computational Aspects of Robot Kinematics, pp. 25-43, Volume 9, No. 1, (1994).
28. N. D. Hemkumar, J. R. Cavallaro, “Simulation of Systolic Arrays on the Connection Machine,” SCS Simulation, Special Issue on High Performance Computing, pp. 151-159, Volume 61, No. 3, (September 1993).
29. K. Kota, J. R. Cavallaro, “Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors,” IEEE Transactions on Computers, pp. 769-779, Volume 42, No. 7, (July 1993).
30. J. R. Cavallaro, F. T. Luk, “CORDIC Arithmetic for an SVD Processor,” Journal of Parallel and Distributed Computing, pp. 271-290, Volume 5, No. 3, (June 1988).
1. M. L. Leuschen, I. D. Walker, and J. R. Cavallaro “Nonlinear Fault Detection for Hydraulic Systems,” Fault Diagnosis and Fault Tolerance for Mechatronic Systems, Recent Advances, (F. Caccavale and Luigi Villani, Eds.), (Springer Tracts in Advanced Robotics Volume I, (B. Siciliano, O. Khatib, and F. Groen, Series Eds.), Springer-Verlag, Berlin Heidelberg, Germany, pp. 169-191, 2003
2. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Chapter 3: Robotic Fault Tolerance: Algorithms and Architectures,” Robotics and Remote Systems in Hazardous Environments, (M. Jamshidi and P. J. Eicker, Eds.), Prentice Hall, Englewood Cliffs, NJ, pp. 53-73, 1993.
1. G. Xu, J. R. Cavallaro, B. Aazhang, “VLSI Implementation of the Differencing Multistage Detection in CDMA Communication Systems,” U.S. patent number 6529495, (Issued March 4, 2003), Chinese patent CN1310888T, European Union patent EP1101290.
2. G. Szabó, M. Kido, J. R. Cavallaro, F. K. Tittel, “Interferometric Phase Shifting Method for High Resolution Microlithography,” U.S. Patent number 5458999, (Issued October 17, 1995).
1. S. Rajagopal, S. Rixner, J. R. Cavallaro, “A Programmable Baseband Processor Design for Software Defined Radios”, IEEE Midwest Conference on Circuits and Systems, pp. 413-416, Tulsa, OK, (August 2002).
2. S. Das, S. Rajagopal, C. Sengupta, J. R. Cavallaro, “Arithmetic Acceleration Techniques for Wireless Communication Receivers,” 33rd Asilomar Conference on Signal, Systems, and Computers, pp. 1469-1474, Pacific Grove, CA (October 1999).
3. G. Xu, J. R. Cavallaro, “Real-Time Implementation of the Multistage Algorithm for Next-Generation Wideband CDMA Systems,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations IX, Volume 3807, pp. 62-73, Denver, CO (July 1999).
4. M. L Leuschen, J. R. Cavallaro, I. D. Walker, “Monitoring and Diagnostics for a Hydraulic Robot in Hazardous Environments,” Proc. Eighth ANS Topical Meeting on Robotics and Remote Systems, Pittsburgh, PA (April 1999).
5. B. Haller, J. Götze, J. R. Cavallaro, “Efficient Implementation of Rotation Operations for High-Performance QRD-RLS Filtering,” Proc. IEEE International Conference on Application-specific Systems, Architectures, and Processors, (ASAP), pp. 162-174, Zurich, Switzerland (July 1997), Awarded Best Paper Award.
6. J. R. Cavallaro, I. D. Walker, “Failure Mode Analysis of a Proposed Manipulator-based Hazardous Material Retrieval System,” Proc. American Nuclear Society 7th Topical Meeting on Robotics and Remote Systems, Vol. 2, pp. 1096-1102, Augusta, GA (April 1997).
7. J. R. Cavallaro, C. Sengupta, F. K. Tittel, W. L. Wilson, Jr., “Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations,” Proc. of the NSF Design and Manufacturing Grantees Conference, SME Press, pp. 345-346, Albuquerque, NM (January 1996).
8. J. R. Cavallaro, F. K. Tittel, W. L. Wilson, Jr., “Submicron Optical Microlithography Based on Interferometric Phase Shifting,” Proc. of the NSF Design, Manufacturing and Industrial Innovation Grantees Conference, SME Press, pp. 395-396, San Diego, CA (January 1995).
9. D. L. Hamilton, M. L. Visinsky, J. K. Bennett, J. R. Cavallaro, I. D. Walker, “Fault Tolerant Algorithms and Architectures for Robotics,” Proc. IEEE Mediterranean Electrotechnical Conference, pp. 1034-1036, Antalya, Turkey (April 1994).
10. J. R. Cavallaro, I. D. Walker, “A Survey of NASA and Military Standards on Fault Tolerance and Reliability Applied to Robotics,” Proc. AIAA/NASA Conference on Intelligent Robots in Field, Factory, Service, and Space (CIRFFSS'94), pp. 282-286, Houston, TX (March 1994).
11. H. M. Fossati, F. K. Tittel, W. L. Wilson, J. R. Cavallaro, “Enhanced VLSI Manufacturability using an Integrated CAD Framework,” Proc. of the NSF Design and Manufacturing Grantees Conference, SME Press, pp. 549-550, Boston, MA (January 1994).
12. M. Kido, J. R. Cavallaro, G. Szabó, W. L. Wilson, F. K. Tittel, “A New Phase Shifting Method for High Resolution Microlithography,” Proc. of the NSF Design and Manufacturing Grantees Conference, SME Press, pp. 577-578, Boston, MA (January 1994).
13. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Expert System Framework of Fault Detection and Fault Tolerance for Robots,” Proc. Fourth International Symposium on Robotics and Manufacturing, ASME Press Series on Robotics and Manufacturing, Volume 4, pp. 793-799, Sante Fe, NM (November 1992).
1. “A Software Simulation Testbed for Third Generation CDMA Wireless Systems,” National Instruments NI-Week, Austin, TX (August 17, 2004).
2. “Architectures, Algorithms, and Research Platforms for Wireless Communication,” Univ. of Oulu, Finland (June 15, 2004).
3. “Advanced Algorithms, Architectures, and Implementations for W-CDMA and WLAN Communication Systems,” (Short Course with B. Aazhang), Univ. of Oulu, Finland (August 12-14, 2002).
4. “Reconfigurable VLSI Communication Processor Architectures” Workshop on Future Wireless Communication Systems and Algorithms, University of Oulu, Oulu, Finland (August 12, 2002).
5. “Architectures for Heterogeneous Multi-tier Wireless Networks,” Panelist, Third Strategic Workshop on Wireless Communications, Rebild, Denmark (September 9, 2001).
6. “Scheduling of Advanced Communication Receiver Algorithms on Custom VLSI Architectures,” Hewlett Packard VLSI Laboratory, Fort Collins, CO (July 19, 2001).
7. “VLSI Architectures for Multi-tier Wireless Networks,” Hewlett Packard VLSI Laboratory, Fort Collins, CO (July 18, 2001).
8. “Rice Everywhere Network (RENE)” University of Oulu, Oulu, Finland (June 15, 2001).
9. “VLSI Architectures for Multi-tier Wireless Systems.” University of Queensland, Brisbane, Australia (May 14, 2001).
10. “VLSI Architectures for Multi-tier Wireless Systems,” Lulea University of Technology, Lulea, Sweden (August 20, 2000).
11. “VLSI Architectures for Multi-tier Wireless Systems,” University of Michigan, EECS Dept., Ann Arbor, MI (November 9, 1999).
12. “Overview of Implementation Issues for Multi-tier Networks on DSPs,” Berkeley Wireless Research Center, Berkeley, CA (October 22, 1999).
13. “Overview of Implementation Issues for Multi-tier Networks on DSPs,” KTH Royal Institute of Technology, Stockholm, Sweden (August 19, 1999).
14. “Overview of Implementation Issues for Multi-tier Networks on DSPs,” Helsinki University of Technology, Helsinki, Finland, (August 18, 1999).
15. “Overview of Implementation Issues for Multi-tier Networks on DSPs,” University of Oulu, Oulu, Finland (August 16, 1999).
16. “Multiuser Techniques for Channel Estimation and Detection for CDMA Systems,” Texas Instruments TMS320 Educators Conference, Houston, TX (with C. Sengupta, J. R. Cavallaro, B. Aazhang, et al., August 1998).
17. “Architectures and Signal Processing Algorithms for CDMA Communications,” Nokia Corporation, San Diego, CA (Short Course with B. Aazhang, September 26-27, 1996).
18. “Architectures and Signal Processing Algorithms for CDMA Communications,” Nokia Research Center, Helsinki, Finland (Short Course with B. Aazhang, August 28-29, 1996).
19. “Parallel VLSI/DSP Architectures for CDMA Communication Systems,” Department of Electrical Engineering, Swiss Federal Institute of Technology (ETH), Zürich, Switzerland (July 18, 1995).
20. “VLSI CORDIC Co-Processors for DSP,” Texas Instruments, Houston, TX (January 26, 1993).
21. “CORDIC Parallel Processor Architectures for an SVD Processor,” IBM Almaden Research Center, San Jose, CA (July 21, 1989).
22. “CORDIC Algorithms for Digital Signal Processing,” Texas Instruments, Houston, TX (July 7, 1989).
23. “VLSI Implementation of a CORDIC SVD Processor,” Mitre Corporation, Bedford, MA (June 14, 1989).
1. Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, “Efficient MIMO Equalization for Downlink Multi-Code CDMA: Complexity Optimization and Comparative Study,” IEEE Globecom, Dallas, TX, (Accepted, November 2004).
2. A. de Baynast, P. Radosavljevic, J. R. Cavallaro, “Chip level LMMSE Equalization for Downlink MIMO CDMA in Fast Fading Environments,” IEEE Globecom, Dallas, TX, (Accepted, November 2004).
3. Y. Guo, D. McCain, J. R. Cavallaro, “Low Complexity System-On-Chip Architectures of Optimal Parallel-Residue-Compensation In CDMA Systems,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada (May 2004).
4. M. Karkooti and J. Cavallaro, “Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding,” Proc. IEEE International Conference on Information Technology (ITCC), pp. 579-585, Volume 1, Las Vegas, NV (April 2004).
5. V. Chandrasekhar, F. Livingston, J. R. Cavallaro, “Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers,” Proc. IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 251-261, The Hague, The Netherlands (June 2003).
6. Y. Guo, G. Xu, D. McCain, J. R. Cavallaro, “Rapid Scheduling of Efficient FPGA Architectures for Next-Generation HSDPA Wireless System Using Precision C Synthesizer,” Proc. 14th IEEE International Workshop on Rapid Systems Prototyping (RSP 2003), pp. 179-185, San Diego, CA, (June 2003).
7. P. Murphy; J. P. Frantz, E. Welsh; R. Hardy, T. Mohsenin, J. R. Cavallaro, “VALID: Custom ASIC Verification and FPGA Education Platform” Proc. 2003 IEEE International Conference on Microelectronic Systems Education, pp. 66-67, Anaheim, CA, (June 2003).
8. J. R. Cavallaro, M. Vaya, “VITURBO: A Reconfigurable Architecture for Viterbi and Turbo Decoding,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp.497-500, Volume II, Hong Kong, China (April 2003).
9. Y. Guo, J. R. Cavallaro, “Enhanced Power Efficiency of Mobile OFDM Radio using Predistortion and Post-Compensation,” Proc. IEEE 56th Vehicular Technology Conference, pp. 214-218, Vancouver, BC, Canada (September 2002).
10. M. L. Leuschen, I. D. Walker, and J. R. Cavallaro, “Nonlinear Fault Detection for Hydraulics”, Recent Advances in Fault Diagnosis and Fault Tolerance for Mechatronic Systems, in Proc. 17th IEEE International Symposium on Intelligent Control, Vancouver, BC, Canada (October 2002).
11. Y. Guo, J. R. Cavallaro, “Post-Compensation Of RF Non-Linearity In Mobile OFDM Systems By Estimation Of Memory-Less Polynomial, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 217-220, Volume I, Scottsdale, AZ (May 2002).
12. F. Livingston, V. Chandrasekhar, M. Vaya, J. R. Cavallaro, “Handset Detector Architectures for DS-CDMA Wireless Systems”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 265-268, Volume III, Scottsdale, AZ (May 2002).
13. Y. Guo, J. R. Cavallaro, “A Novel Adaptive Pre-Distorter Using LS Estimation Of SSPA Non-Linearity In Mobile OFDM Systems”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 453-456, Volume III, Scottsdale, AZ (May 2002).
14. M. L. Leuschen, I. D. Walker, J. R. Cavallaro. "Robotic Fault Detection Using Nonlinear Analytical Redundancy", Proc. IEEE International Conference on Robotics and Automation, pp. 456-463, Washington, DC (May 2002).
15. S. Rajagopal, J. R. Cavallaro, “On-line Arithmetic for Detection in Digital Communication Receivers,” Proc. IEEE International Symposium on Computer Arithmetic, pp. 257-265, Vail, CO (June 2001).
16. S. Rajagopal, J. R. Cavallaro, “A Bit-streaming Pipelined Multiuser Detector for Wireless Communications,” Proc. IEEE International Symposium on Circuits and Systems, Sydney, Australia, pp. 128-131, Volume IV, Sydney, Australia (May 2001).
17. S. Das, E. Erkip, J. R. Cavallaro, and B. Aazhang, “Maximum Weight Basis Decoding of Convolutional Codes,” Proc. IEEE Global Telecommunications Conference (Globecom), pp. 835-841, Volume 2, San Francisco, CA (November 2000).
18. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, R. G. Gamache, M. Martin, “Experimental AR Fault Detection Methods for a Hydraulic Robot,” Proc. 18th International System Safety Conference, pp. 402-409, Fort Worth, TX (Sept. 2000).
19. S. Rajagopal, S. Bhashyam, J. R. Cavallaro, B. Aazhang, “Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers,” IEEE 12th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 173-184, Boston, MA (July 2000).
20. I. D. Walker, J. R. Cavallaro, M. L. Leuschen, “Keeping the Analog Genie in the Bottle: A Case for Digital Robots,” IEEE International Conference on Robotics and Automation, pp.1063-1070,Detroit, MI (May 1999).
21. M. L. Visinsky, I. D. Walker, J. R. Cavallaro, “New Dynamic Model-Based Fault Detection Thresholds for Robot Manipulators,” Proc. IEEE International Conference on Robotics and Automation, pp. 1388-1395, San Diego, CA (May 1994).
22. N. D. Hemkumar, J. R. Cavallaro, “Efficient Complex Matrix Transformations with CORDIC,” Proc. IEEE 11th Symposium on Computer Arithmetic, pp. 122-129, Windsor, Ontario, Canada (June 1993).
23. M. L. Visinsky, I. D. Walker, J. R. Cavallaro, “Layered Dynamic Fault Detection and Tolerance,” Proc. IEEE International Conference on Robotics and Automation, Volume 2, pp. 180-187, Atlanta, GA (May 1993).
24. I. D. Walker, J. R. Cavallaro, “Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots,” Proc. IEEE International Conference on Robotics and Automation, Volume 1, pp. 870-877, Atlanta, GA (May 1993).
25. J. R. Cavallaro, F. T. Luk, “CORDIC Arithmetic for an SVD Processor,” Proc. IEEE 8th Symposium on Computer Arithmetic, pp. 113-120, Como, Italy, (May 1987).
1. P. Radosavljevic, J. Cavallaro, A. de Baynast, “ASIP Architecture Implementation of Channel Equalization Algorithms for MIMO Systems in WCDMA Downlink,” IEEE Vehicular Technology Conference (VTC), (Accepted, September 2004).
2. Y. Guo, D. McCain, J. Zhang J. R. Cavallaro, “Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink,” Proc. 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, (November 2003).
3. Y. Guo, J. R. Cavallaro, “Reducing Peak-to-Average Power Ratio in OFDM Systems by Adaptive Dynamic Range Companding,” 3G Wireless, World Wireless Congress, paper 159, pp. 536-541, San Francisco, CA (May, 2002).
4. Y. Guo, H. Zhang, X. Wang, and Joseph R. Cavallaro, “VLSI Implementation for Mallat's Fast DWT Algorithm with Reduced Complexity,” IEEE Global Telecommunications Conference (Globecom), Volume 1, pp. 320-324, San Antonio, TX (November 2001).
5. K. Chadha and J. R. Cavallaro, “A Dynamically Reconfigurable Viterbi Decoder Architecture,” 35rd Asilomar Conference on Signal, Systems, and Computers, Volume 1, pp. 66-71, Pacific Grove, CA (November 2001).
6. S. Rajagopal, B. A. Jones and J. R. Cavallaro, “Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs,” International Conference on Signal Processing Applications and Technology (ICSPAT), Dallas, TX, (October 2000) (Best paper award).
7. V. Sundaramurthy, J. R. Cavallaro, “A Software Simulation Testbed for Third Generation CDMA Wireless Systems,” 33rd Asilomar Conference on Signal, Systems, and Computers, pp. 1680-1684, Pacific Grove, CA (October 1999).
8. C. Sengupta, S. Das, J. R. Cavallaro, B. Aazhang, “Efficient Multiuser Receivers for CDMA Systems,” IEEE Wireless Communications and Networking Conference, pp. 1459-1463, New Orleans, LA (September 1999).
9. C. Carreras, I. D. Walker, O. Nieto, J. R. Cavallaro, “Robot Reliability Estimation using Interval Methods,” MISC’99 Workshop on Applications of Interval Analysis to Systems and Control, pp. 371-385, Girona, Spain (February 1999).
10. M. Leuschen, I. D. Walker, J. R. Cavallaro, “Investigation of Reliability of Hydraulic Robots for Hazardous Environments using Analytic Redundancy,” IEEE Annual Reliability and Maintainability Symposium, pp. 122-128,Washington, DC (January 1999).
11. S. Das, E. Erkip, J. R. Cavallaro, B. Aazhang, “Iterative Multiuser Detection and Decoding,” IEEE 7th Communication Theory Mini-Conference; in conjunction with Globecom, pp. 249-254, Sydney, Australia (November 1998).
12. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Maximum Likelihood Multipath Channel Parameter Estimation in CDMA Systems using Antenna Arrays,” Proc. 9th IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), CD-ROM Paper 398J017, Boston, MA (September 1998).
13. C. Sengupta, S. Das, J. R. Cavallaro, B. Aazhang, “Fixed Point Error Analysis of Multiuser Detection and Synchronization Algorithms for CDMA Communication Systems,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Volume 6, pp. 3249-3252, Seattle, WA (April 1998).
14. M. Leuschen, I. D. Walker, J. R. Cavallaro, “Fuzzy Markov Modeling for Robot Reliability,” Proc. IEEE Annual Reliability and Maintainability Symposium, pp. 209-214, Anaheim, CA (January 1998).
15. S. Das, J. R. Cavallaro, B. Aazhang, “Computationally Efficient Multiuser Detectors,” Proc. 8th IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), pp. 62-67, Helsinki, Finland (September 1997).
16. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Tracking Fading Multipath Channel Parameters in CDMA Systems using a Subspace Based Method - An Implementation Perspective,” Proc. 8th IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), pp. 734-739, Helsinki, Finland (September 1997).
17. C. Sengupta, J. R. Cavallaro, B. Aazhang, “Solving the SVD Updating Problem for Subspace Tracking on a Fixed Sized Linear Array of Processors,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Volume 5, pp. 4137-4140, Munich, Germany (April 1997).
18. B. M. Harpel, J. B. Dugan, I. D. Walker, J. R. Cavallaro, “Analysis of Robots for Hazardous Environments,” Proc. IEEE Annual Reliability and Maintainability Symposium, pp. 111-116, Philadelphia, PA (January 1997).
19. I. D. Walker, J. R. Cavallaro, “The Use of Fault Trees for the Design of Robots for Hazardous Environments,” Proc. IEEE Annual Reliability and Maintainability Symposium, pp. 229-235, Las Vegas, NV (January 1996).
20. K. Kota, J. R. Cavallaro, “A Normalization Scheme to Reduce Numerical Errors in Inverse Tangent Computations on a Fixed-Point CORDIC Processor,” Proc. IEEE International Symposium on Circuits and Systems, pp. 244-247, San Diego, CA (May 1992).
21. N. D. Hemkumar, J. R. Cavallaro, “A Systolic VLSI Architecture for Complex SVD,” Proc. IEEE International Symposium on Circuits and Systems, pp. 1061-1064, San Diego, CA (May 1992).
22. J. R. Cavallaro, C. D. Near, M. Ü. Uyar, “Fault-Tolerant VLSI Processor Array for the SVD,” Proc. IEEE International Conference on Computer Design, pp. 176-180, Cambridge, MA (October 1989).
23. J. R. Cavallaro, F. T. Luk, “Floating-Point CORDIC for Matrix Computations,” Proc. IEEE International Conference on Computer Design, pp. 40-42, Rye Brook, NY (October 1988).
1. J. R. Cavallaro, M. C. Brogioli, A. de Baynast, and P. Radosavljevic, “Reconfigurable Architectures for Wireless Systems: Design Exploration and Integration Challenge,” Wireless World Research Forum (WWRF-12), Toronto, Canada (November 2004).
2. J. R. Cavallaro, P. Radosavljevic, “ASIP Architecture for Future Wireless Systems: Flexibility and Customization,” Wireless World Research Forum (WWRF-11), Oslo, Norway (June 2004).
3. M. L. Leuschen, J. R. Cavallaro, I. D. Walker, “Testing on the Curve: Nonlinear Analytical Redundancy for Fault Detection,” Proc. Ninth ANS Topical Meeting on Robotics and Remote Systems, Session 22, Paper F131, Seattle, WA (March 2001).
4. J. R. Cavallaro, “Wireless Networks,” Proc. Workshop On Strategic Research Plan for New Millennium Wireless World, Cagliari, Sardinia, Italy (May 2000).
5. J. R. Cavallaro, “VLSI Architectures for Multi-tier Wireless Systems,” Proc Collaborative Technologies Workshop, Air Force Research Laboratory, Oakland University, pp. 28-31, Rochester, MI (November 1999).
6. S. Das, S. Bhashyam, J. R. Cavallaro, B. Aazhang, “Partially Blind Multiuser Detection,” Proc. Conference on Information Sciences and Systems,pp. 650-655, Baltimore, MD, (March 1999).
7. C. Sengupta, S. Das, J. R. Cavallaro, B. Aazhang, “Joint Multiuser Channel Estimation and Detection for CDMA Systems,” Proc. IT Workshop on Detection, Estimation, Classification, and Imaging, Santa Fe, NM (February 1999).
8. S. Das, C. Sengupta, J. R. Cavallaro, “Hardware Design Issues for a Mobile Unit for Next Generation CDMA Systems,” Proc. SPIE Conference on Advanced Signal Processing: Algorithms, Architectures, and Implementations VIII, Volume 3461, pp. 476-487, San Diego CA (July 1998).
9. C. Sengupta, A. Hottinen, J. R. Cavallaro, B. Aazhang, “Maximum Likelihood Multipath Channel Parameter Estimation in CDMA Systems,” Proc. Conference on Information Sciences and Systems, Volume 1, pp. 6-11, Princeton, NJ (March 1998,).
10. S. Das, J. R. Cavallaro, B. Aazhang, “Fast Multiuser Detector for a Time Varying CDMA System,” Proc. SPIE Conference on Advanced Signal Processing: Algorithms, Architectures, and Implementations VII, Volume 3162, pp. 569-580, San Diego, CA (July 1997).
11. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Robot Reliability Using Fuzzy Fault Trees and Markov Models,” Proc. SPIE Conference on Sensor Fusion and Distributed Robotic Agents, Volume 2905, pp. 73-91, Boston, MA (November 1996).
12. C. Sengupta, K. Kota, J. R. Cavallaro, “Parallel Algorithms and Architectures for Subspace-based Channel Estimation for CDMA Communication Systems,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations VI, Volume 2846, pp. 412-423, Denver, CO (August 1996).
13. D. L. Hamilton, J. R. Cavallaro, I. D. Walker, “Risk and Fault Tolerance for Robotics and Manufacturing,” Proc. 1996 IEEE Mediterranean Electrotechnical Conference, pp. 250-255, Bari, Italy (May 1996).
14. B. Haller, B. Aazhang, J. R. Cavallaro, “Near-Far Resistant Code Synchronization for CDMA Systems – An Implementation Perspective,” Proc. 3rd International Conference on Telecommunications (ICT), Volume 1, pp. 441-448, Istanbul, Turkey (April 1996).
15. M. Erdélyi, Zs. Bor, G. Szabó, J. R. Cavallaro, M. C. Smayling, F. K. Tittel, W. L. Wilson, Jr., “Sub-quarter Micron Contact Hole Fabrication Using Annular Illumination,” Proc. SPIE Conference on Optical Microlithography IX, Volume 2726, pp. 88-93, Santa Clara, CA (March 1996).
16. C. Sengupta, M. Erdélyi, J. R. Cavallaro, M. C. Smayling, F. K. Tittel, W. L. Wilson, Jr., “An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators,” Proc. SPIE Conference on Optical Microlithography IX, Volume 2726, pp. 244-252, Santa Clara, CA (March 1996).
17. J. R. Cavallaro, I. D. Walker, “Protective Operating System Shell Environment for Robots,” Proc. SPIE Sensor Fusion and Networked Robotics VIII, Volume 2589, pp. 194-205, Philadelphia, PA (October 1995).
18. F. K. Tittel, M. Erdélyi, C. Sengupta, Zs. Bor, G. Szabó, J. R. Cavallaro, M. C. Smayling, W. L. Wilson, Jr., “Ultrahigh Resolution Lithography with Excimers,” NATO Workshop on Gas Lasers - Recent Developments and Future Prospects, Kluwer Academic Publishers, pp. 263-272, Moscow, Russia (July 1995).
19. F. K. Tittel, J. R. Cavallaro, M. Kido, M. C. Smayling, C. Sengupta, G. Szabó, W. L. Wilson, Jr., “A New Interferometric Shifting Technique for Sub-halfmicron Laser Microlithography,” Proc. SPIE Conference on Optical/Laser Microlithography VIII, Volume 2440, pp. 827-837, Santa Clara, CA (February 1995).
20. F. K. Tittel, J. R. Cavallaro, M. Kido, M. C. Smayling, G. Szabó, W. L. Wilson, Jr., “A New Phase Shifting Technique for Deep UV Excimer Laser Based Lithography,” Proc. SPIE Photonics West, Volume 2380, pp. 195-202, San Jose, CA (February 1995).
21. F. K. Tittel, J. R. Cavallaro, M. Kido, M. C. Smayling, G. Szabó, W. L. Wilson, Jr., “Interferometric Phase Shift Technique for High Resolution Microlithography,” Proc. SPIE Tenth International Symposium on Gas Flow and Chemical Lasers, Volume 2502, pp. 617-624, Friedrichshafen, Germany (September 1994).
22. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Adaptive Fault Detection and Tolerance for Robots,” Proc. First World Automation Conference, TSI Press, pp. 205-210, Wailea, HI (August 1994).
23. K. Kota, J. R. Cavallaro, “Pipelining Multiple SVDs on a Single Processor Array,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations V, Volume 2296, pp. 612-623, San Diego, CA (July 1994).
24. N. D. Hemkumar, J. R. Cavallaro, “Jacobi-like Matrix Factorizations with CORDIC-based Inexact Diagonalizations,” Proc. Fifth SIAM Conference on Applied Linear Algebra, pp. 295-299, Snowbird, UT (June 1994).
25. M. Kido, J. R. Cavallaro, W. L. Wilson, Jr., F. K. Tittel, “A New Phase Shifting Method for High Resolution Microlithography,” Proc. SPIE Conference on Optical/Laser Microlithography VII, Volume 2197, pp. 835-843, San Jose, CA (March 1994).
26. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “Dynamic Sensor-Based Fault Detection for Robots,” Proc. SPIE Conference on Cooperative Intelligent Robotics in Space IV, Volume 2057, pp. 385-396, Boston, MA (September 1993).
27. K. Kota, J. R. Cavallaro, “CMOS Processor Element for a Fault-Tolerant SVD Array,” Proc. SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Implementations IV, Volume 2027, pp. 483-494, San Diego, CA (July 1993).
28. I. D. Walker, J. R. Cavallaro, “Dynamic Fault Reconfigurable Intelligent Control Architectures for Robotics,” Proc. Fifth ANS Topical Meeting on Robotics and Remote Systems, pp. 305-311, Knoxville, TN (April 1993).
29. N. D. Hemkumar, J. R. Cavallaro, “Simulation of Systolic Arrays on the Connection Machine,” Proc. SCS International Simulation Technology Conference (SimTec), pp. 83-88, Clear Lake, TX (November 1992), (received Best Student Paper Award).
30. M. L. Visinsky, I. D. Walker, J. R. Cavallaro, “Fault Detection and Fault Tolerance in Robotics,” Proc. 1991 NASA Space Operations, Applications, and Research Symposium, pp. 262-271, Houston, TX (July 1991).
31. N. D. Hemkumar, K. Kota, J. R. Cavallaro, “CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing,” Proc. Ninth Biennial University/Government/Industry Microelectronics Symposium, IEEE Press, pp. 64-69, Melbourne, FL (June 1991).
32. A. S. Deo, J. R. Cavallaro, I. D. Walker, “New Real-Time Robot Motion Algorithms using Parallel VLSI Architectures,” Proc. Fifth SIAM Conference on Parallel Processing for Scientific Computing, pp. 369-375, Houston, TX (March 1991).
33. I. D. Walker, J. R. Cavallaro, “Parallel VLSI Architectures for Real-Time Control of Redundant Robots,” Proc. Fourth ANS Topical Meeting on Robotics and Remote Systems, pp. 299-309, Albuquerque, NM (February 1991).
34. J. R. Cavallaro, A. C. Elster, “A CORDIC Processor Array for the SVD of a Complex Matrix,” Proc. 2nd International Workshop on SVD and Signal Processing, pp. 66-73, Kingston, RI (June 1990), and Proc. SVD and Signal Processing, II; Algorithms, Analysis and Applications, Elsevier Science Publishers B.V., pp. 227-239, (1991).
35. J. R. Cavallaro, M. P. Keleher, R. H. Price, G. S. Thomas, “VLSI Implementation of a CORDIC SVD Processor,” Proc. Eighth Biennial University/Government/Industry Microelectronics Symposium, IEEE Press, pp. 256-260, Westborough, MA (June 1989).
36. J. R. Cavallaro, F. T. Luk, “Architectures for a CORDIC SVD Processor,” Proc. SPIE Real-Time Signal Processing IX, Volume 698, pp. 45-53, San Diego, CA (August 1986).
37. D. J. Aneshansley, C. Pottle, J. R. Cavallaro, “Laboratory Workstations in Electrical Engineering,” Proc. IBM Academic Information Systems Advanced Education Projects (AEP) Conference, pp. 211-229, Alexandria, VA (June 1985).
1. S. Rajagopal, S. Rixner, J. R. Cavallaro, “Reconfigurable Stream Processors for Wireless Base-stations,” Dept. of Electrical and Computer Engineering, Technical Report TREE0305, Rice Univ., Houston, TX (October 2003).
2. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Nonlinear Analytical Redundancy Tests for a Hydraulic Manipulator,” Dept. of Electrical and Computer Engineering, Technical Report TREE0101, Rice Univ., Houston, TX (January 2001).
3. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Analytical Redundancy Data Analysis of a Hydraulic Robot Testbed,” Dept. of Electrical and Computer Engineering, Technical Report TREE9911, Rice Univ., Houston, TX (December 1999).
4. J. R. Kincaid, I. D. Walker, J. R. Cavallaro, “Problems and Considerations in Fault Tree Analysis,” Dept. of Electrical and Computer Engineering, Technical Report TREE9513, Rice Univ., Houston, TX (October 1995).
5. J. R. Cavallaro, I. D. Walker, “Layered Dynamic Fault Detection and Tolerance for Robots,” in Research on Robotics by Principal Investigators of the Robotics Technology Development Program, R. W. Harrigan, Ed., Sandia National Laboratories Report, SAND94-0844, Albuquerque, NM (March 1995).
6. K. Kota, J. R. Cavallaro, “Parallel Architectures for CDMA Synchronization,” Dept. of Electrical and Computer Engineering, Technical Report TREE9409, Rice Univ., Houston, TX (March 1994).
7. I. D. Walker, J. R. Cavallaro, “Failure Mode Analyses of the Hanford Manipulator,” Dept. of Electrical and Computer Engineering, Technical Report 9402, Rice Univ., Houston, TX (March 1994).
8. N. D. Hemkumar, J. R. Cavallaro, “Efficient Matrix Factorizations with Inexact Diagonalizations,” Dept. of Electrical and Computer Engineering, Technical Report TREE9306, Rice Univ., Houston, TX (September 1993).
9. N. D. Hemkumar, J. R. Cavallaro, “Redundant and On-Line CORDIC for Complex Matrix Transformations,” Dept. of Electrical and Computer Engineering, Technical Report TREE9301, Rice Univ., Houston, TX (March 1993).
10. N. D. Hemkumar, J. R. Cavallaro, “An Efficient Parallel Implementation of the Jacobi SVD Algorithm for Arbitrary Matrices,” Dept. of Electrical and Computer Engineering, Technical Report TREE9212, Rice Univ., Houston, TX (September 1992).
11. M. L. Visinsky, J. R. Cavallaro, I. D. Walker, “A Dynamic Fault Tolerance Framework for Remote Robots,” Dept. of Electrical and Computer Engineering, Technical Report TREE9211, Rice Univ., Houston, TX (August 1992).
12. M. L. Visinsky, I. D. Walker, J. R. Cavallaro, “Fault Detection and Fault Tolerance in Robotics,” Dept. of Electrical and Computer Engineering, Technical Report TREE9102, Rice Univ., Houston, TX (February 1991).
13. J. R. Cavallaro, I. D. Walker, “Inverse Kinematic VLSI Architectures for Redundant Robots with On-Line CORDIC,” Dept. of Electrical and Computer Engineering, Technical Report TREE9004, Rice Univ., Houston, TX (February 1990).
14. J. R. Cavallaro, A. C. Elster, “Complex Matrix Factorizations with CORDIC Arithmetic,” SIAM Conference on Approximation Theory and Numerical Linear Algebra, Kent State Univ., Kent, OH (April 1, 1989), and Technical Report TR89-1071, Dept. of Computer Science, Cornell Univ., Ithaca, NY (December 1989).
1. S. Rajagopal, S. Rixner, J. R. Cavallaro, B. Aazhang, “DSP Architectural Considerations for Optimal Baseband Processing,” Texas Instruments TMS320 Educators Conference, Houston, TX (August 2002).
2. B. A. Jones, S. Rajagopal, J. R. Cavallaro, “Real-Time DSP Multiprocessor Implementation for Future Wireless Base-Stations,” Texas Instruments TMS320 Educators Conference, Houston, TX (August 3, 2000).
3. S. Rajagopal, G. Xu, J. R. Cavallaro, “Implementation of Channel Estimation and Multiuser Detection Algorithms for W-CDMA on Digital Signal Processors,” Texas Instruments TMS320 Educators Conference, Houston, TX (August 5, 1999).
4. I. D. Walker, J. R. Cavallaro, “Failure Modes Tutorial,” IEEE International Conference on Robotics and Automation, Albuquerque, NM (April 1997).
5. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” Seventh DOE Forum on Robotics for Environmental Restoration and Waste Management, Albuquerque, NM (July 24, 1996).
6. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” DOE CCAT Environmental Restoration Review Panel, Albuquerque, NM (February 20, 1996).
7. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” Sixth DOE Forum on Robotics for Environmental Restoration and Waste Management, Albuquerque, NM (August 17, 1995).
8. M. Erdélyi, Zs. Bor, F. K. Tittel, J. R. Cavallaro, G. Szabó, W. L. Wilson, Jr., M. Smayling, C. Sengupta, “A Phase Shifting Technique for Ultrahigh Resolution Deep-UV Lithography,” First International Symposium on 193 nm Lithography, Colorado Springs, CO (August 15, 1995).
9. J. R. Cavallaro, B. Aazhang, K. Kota, C. Sengupta, “Parallel Algorithms for CDMA Communication Systems,” Fifth Annual Texas Instruments TMS320 Educators Conference, Houston, TX (August 11, 1995).
10. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” DOE CCAT Environmental Restoration Review Panel, Albuquerque, NM (February 21, 1995).
11. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” Fifth DOE Forum on Robotics for Environmental Restoration and Waste Management, Albuquerque, NM (August 31, 1994).
12. M. Kido, G. Szabó, J. R. Cavallaro, W. L. Wilson, Jr., M. C. Smayling, F. K. Tittel, “Advanced High Resolution Interferometric Phase Shift Technique for Microlithography,” Conference on Lasers and Electro-Optics, Volume 8, Optical Society of America Technical Digest Series, p. 395, Anaheim, CA (May 1994).
13. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” DOE CCAT Environmental Restoration Review Panel, Albuquerque, NM (February 23, 1994).
14. J. R. Cavallaro, I. D. Walker, “Real-Time Kinematics of Redundant Robots Using a CORDIC DSP Architecture,” Third Annual Texas Instruments Educators Conference, Volume 2, pp. 185-191, Houston, TX (August 1993).
15. J. R. Cavallaro, I. D. Walker, “Robot Reliability,” DOE Cross-Cutting and Advanced Technology Program Demonstrations, Sandia National Laboratories, Albuquerque, NM (July 21, 1993).
16. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” Fourth DOE Forum on Robotics for Environmental Restoration and Waste Management, Albuquerque, NM (July 21, 1993).
17. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” DOE CCAT Environmental Restoration Review Panel, Dallas, TX (February 9, 1993).
18. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” Los Alamos National Laboratories, Los Alamos, NM (November 10, 1992).
19. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” Sandia National Laboratories, Albuquerque, NM (November 9, 1992).
20. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” Third DOE/Industry/University/Lab Forum on Robotics for Environmental Restoration, Waste Management and Waste Minimization, Albuquerque, NM (July 30, 1992).
21. S. H. Brittain, J. A. Jiskra, D. C. Chung, J. R. Cavallaro, “VLSI Design of an Artificial Neural Network,” Tenth Annual Conference on Biomedical Engineering Research in Houston, p. A84, Houston, TX (March 1992).
22. J. R. Cavallaro, I. D. Walker, “Failure Mode Analyses,” DOE CCAT Environmental Restoration Review Panel, Dallas, TX (February 10, 1992).
23. N. D. Hemkumar, J. R. Cavallaro, “A Fast Parallel Jacobi Algorithm for the SVD of Complex Matrices,” Fourth SIAM Conference on Applied Linear Algebra, pp. A10-A11, Minneapolis, MN (September 11, 1991).
24. I. D. Walker, J. R. Cavallaro, “Fault Tolerant Robotic Architectures and Algorithms,” International Conference on Industrial and Applied Mathematics, p. A225, Washington, DC (July 10, 1991).
25. K. Kota, N. D. Hemkumar, J. R. Cavallaro, “A Multipurpose DSP-VLSI Array for Parallel Matrix Computations in Signal Processing and Robotics,” pp. A20-A21, Fifth SIAM Conference on Parallel Processing for Scientific Computing, Houston, TX (March 25, 1991).
26. J. R. Cavallaro, A. C. Elster, I. D. Walker, “A Parallel VLSI Architecture for Robot Motion Computations,” pp. A41-A42, SIAM Annual Meeting, Chicago, IL (July 18, 1990).
27. J. R. Cavallaro, I. D. Walker, A. C. Elster, “Parallel VLSI Architectures to Increase the Efficiency of Robot Control,” Seventh Parallel Circus, Stanford Univ., Stanford, CA (March 30, 1990).
28. J. R. Cavallaro, “CORDIC VLSI Architectures for Matrix Factorizations such as QR and SVD,” Informal Seminar, Rice Center for Research on Parallel Computation, Rice Univ., Houston, TX (March 20, 1990).
29. J. R. Cavallaro, “VLSI CORDIC Architectures,” Faculty Lecture Series, Dept. of Electrical and Computer Engineering, Rice Univ., Houston, TX (March 14, 1989).
30. L. -M. Ewerbring, D. E. Schimmel, J. R. Cavallaro, F. T. Luk, “A VLSI CORDIC Chip for Computing the Singular Value Decomposition,” 9th Annual Research Review, Cornell Program on Submicrometer Structures (PROSUS), Ithaca, NY (October 1987).
31. J. R. Cavallaro, F. T. Luk, “Architectures for a CORDIC SVD Processor,” 8th Annual Research Review, Cornell Program on Submicrometer Structures (PROSUS), Ithaca, NY (October 1986).
1. “Rice University Robot Arm,” The RiskWorks Review, Arthur D. Little, Inc., Cambridge, MA, p. 1, Volume 1, No. 5, (April/May 1995).
2. “Interferometric Method Promises Sub-half-micron Optical Lithography,” Laser Focus World, Nashua, NH, pp. 24-25, Volume 30, No. 11, (November 1994).