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Professor |
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2319 Alberton Lane |
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Rice University, MS 380 |
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Pearland, TX 77584 |
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Dept. of Electrical & Computer Engineering |
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(281) 412-0133 |
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Houston, TX 77251-1892 |
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(713) 348-4719 |
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(713) 348-6196, Fax |
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August 31, 2004 |
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Cornell University, Ph.D. in Electrical Engineering, August 1988.
Thesis Title: VLSI CORDIC Processor Architectures for the Singular Value Decomposition.
Thesis Advisor: Franklin T. Luk.
Princeton University, M.S. in Electrical Engineering, June 1982.
University of Pennsylvania, B.S. in Electrical Engineering, (magna cum laude), May 1981.
· 2002-Present Rice University, Professor,
· 1994-2002 Rice University, Associate Professor (Tenured), Electrical & Computer Engineering, (Courtesy appointment in Computer Science Department, 2000-Present).
· 1996-1997 National Science Foundation, Program Director, Systems Prototyping and Fabrication Program, MIPS Division, CISE Directorate.
· 1988-1994 Rice University, Assistant Professor, Electrical & Computer Engineering
· 1987-1988 Cornell University, IBM Graduate Fellow
· 1986-1987 Cornell University, Research Assistant
· 1983-1986 Cornell University, Teaching Assistant
· 1981-1983 AT&T Bell Laboratories, MTS, Special Business Services Laboratory
· IEEE Computer Society Distinguished Lecturer, 2004-2006
· IEEE Application-Specific Systems, Architectures and Processors Conference, Best Paper Award, (with B. Haller and J. Götze), 1997.
· IEEE Circuits and Systems Society Chapter of the Year Award, (accepted as Chair of the Houston Chapter), 1996
· Hershel M. Rich Invention Award, Rice Engineering Alumni, 1994
· IEEE Region 5 Award for service as Student Branch Counselor, 1992
· NSF Research Initiation Award, 1989-1992
· IBM Graduate Fellowship, 1987-1988
· AT&T Graduate Study Program, 1981-1982
· Member of Tau Beta Pi and Eta Kappa Nu
· National Merit Scholarship, 1977-1978
· VLSI DSP architectures and parallel algorithms for wireless communications and robotics
· VLSI systems design and microlithography
· Fault-Tolerant robotic and computer systems
· High-speed computer arithmetic
1. “MRI: Development of a National University Wireless Testbed: Rice Configurable Baseband Architecture,” NSF EIA-0321266 (PI) $374,000, 2003-2006, (with B. Aazhang, J. P. Frantz, and A. Sabharhal (Co-PIs), (with O. Takeshita, OSU, and D. Goeckel, Umass, and M. Fitz, UCLA (Collaborators).
2. “Algorithms for Next Generation High Data Rate Wireless Systems,” Nokia Corporation, (Co-PI), $586,047, 2003-2005, (with B. Aazhang (PI), A. Sabharwal (Co-PI).
3. “A Research Platform for Seamless Wireless Networks supporting Multimedia Applications,” Nokia Corporation and Texas Instruments, Inc., (PI), $555,000, 2002-2004, (with B. Aazhang (Co-PI)).
4. “CISE Research Resources: A Comprehensive Multi-tier Wireless Network Development Platform,” NSF EIA-0224458 (PI), $187,244, 2002-2004, (with J. P. Frantz (Co-PI), A. Sabharwal (Co-PI), E. Knightly (Co-PI), B. Aazhang (Co-PI)).
5. “Leadership University: New Applications of DSPs in Networking, Wireless Communications, and Image Processing,” Texas Instruments, Inc., (Co-PI), $1,000,000, 2002-2004, (with C. S. Burrus (PI), B. Aazhang (Co-PI), E. W. Knightly (Co-PI), R. G. Baraniuk (Co-PI), R. Nowak (Co-PI), and M. Orchard (Co-PI)).
6. “VLSI Systems Design Education,” AMD Corporation, (PI), $51,000, 1999-2004.
1. “Signal Processing Algorithms and Architectures for CDMA Systems,” Nokia Corporation, Helsinki, Finland, (Co-PI), $444,528, 2000-2002, (with B. Aazhang (PI)).
2. “Seamless Multi-tier Wireless Networks for Multimedia Applications,” NSF ANI-9979465, (Co-PI), $700,000, 1999-2003, (with B. Aazhang (PI), R.G. Baraniuk (Co-PI), E.W. Knightly (Co-PI), and D.S. Wallach (Co-PI)).
3. “Implementation of W-CDMA Networks: Advanced Mobile and Basestation Receiver Prototyping,” Texas TDTP, (PI), $211,148, 2000-2002, (with D.H. Johnson (co-PI)).
4. “Development of a Testbed for Wireless Multiuser Communication Systems,” Nokia Corporation and Texas Instruments, Inc., (PI), $500,781, 1998-2002 (with B. Aazhang (Co-PI)).
5. “Leadership University: New Applications of DSPs in Networking and Integrated Wireless Sensors,” Texas Instruments, Inc., (Co-PI), $1,000,000, 1999-2001, (with C. S. Burrus (PI), B. Aazhang (Co-PI), E. W. Knightly (Co-PI), and R. G. Baraniuk (Co-PI)).
6. “Development of a High Speed Wireless LAN,” Nokia Corporation, (Co-PI), $241,622, 1999-2000 (with B. Aazhang (PI), E. Erkip (Co-PI), and R.G. Baraniuk (Co-PI)).
7. “Development of Multiuser Transceivers for Wireless CDMA Communications,” Texas Technology Development and Transfer Program. TDTP 003604-044, (Co-PI), $201,336, 1998-1999, (with B. Aazhang (PI)).
8. “A Web-Based Engineering Design Tutor,” A.W. Mellon Foundation, (Co-PI), $570,000, 1998-2000, (with M. Terk (PI) and W. Zwaenepoel (Co-PI)).
9. “Development of Monitoring and Diagnostic Methods for Robots Used in Remediation of Waste Sites,” DOE DE-FG07-97ER14830, (PI), $94,944, 1997-1999, (subcontract via Foster-Miller Technologies, Inc., Latham, NY).
10. “Advanced Signal Processing for Multiuser Wireless Communications,” Texas Advanced Technology Program, TATP 003604-049, (Co-PI), $255,000, 1996-1997, (with B. Aazhang (PI)).
11. “Architectures for Multiuser Detection and Channel Estimation in CDMA Communication Systems,” NSF NCR-9506681, (Co-PI), $303,597, 1995-1999, (with B. Aazhang (PI)).
12. “Dynamic Fault Tolerance Methods for Robotics,” NSF IRI-9526363, (Co-PI), $50,000, 1995-1997, (with I. D. Walker (PI)).
13. “Architectures for Multiuser Detection and Channel Estimation in CDMA Communication Systems,” Nokia Corporation, Helsinki, Finland, (Co-PI), $511,785, 1995-1999, (with B. Aazhang (PI)).
14. “Failure Mode Analyses of the Hanford Manipulator,” DOE Westinghouse Hanford Company DE-AC04-94AL850, (Co-PI), $52,743, 1994-1995, (with I. D. Walker, (PI).
15. “Enhanced VLSI Microelectronics Manufacturability using Closed-Loop Photolithographic Simulation,” NSF Materials Synthesis and Processing Initiative DDM-9202639, (PI), $330,000, 1992-1996, (with F. K. Tittel (Co-PI) and W. L. Wilson, Jr. (Co-PI)).
16. “Dynamic Fault Reconfigurable Robotic System Architectures,” DOE Sandia National Laboratories Contract #18-4379A, (PI), $309,017, 1991-1996, (with I. D. Walker (Co-PI)).
17. “VLSI CORDIC Parallel Processor Architectures for the SVD,” NSF Research Initiation Award MIP-8909498, (PI), $69,400, 1989-1992.
1. “VLSI Architectures for Configurable Communication Systems,” NSF, (PI), (with J.P. Frantz (Co-PI)).
2. “CRI: Shared Resources to Explore Multi-level InterConnect Architectures (MICA),” NSF, (PI), (with K. Mohanram, Y. Massoud, S. Rixner (Co-PIs)).
1. “Advanced Plotting Systems for VLSI Design and Education,” Hewlett-Packard Corporation, $19,000, 2000.
2. “Parallel SVD of Arbitrary Matrices on the CM5,” Army High Performance Computing Research Center, Minneapolis, MN. Access to Connection Machine 5, 1992-1995.
3. Texas Instruments, Houston, TX. TMS320 Digital Signal Processing Hardware and Software, 1991-Present.
4. Technology Modeling Associates, Palo Alto, CA. DEPICT Photolithography Simulation Software, 1991-1995.
· Elec 422, VLSI Design I
· Elec 423, VLSI Design II
· Elec 437/630, Multi-tier Wireless Networks (team project course)
· Elec 522, Advanced VLSI Design
· Elec 525, Advanced Computer Architecture
· Elec 625, High Performance Processor Design (with J. K. Bennett)
· Elec 693, 694, Advanced Topics Seminars - Computer Systems
· Elec 490, Senior Independent Projects
· Elec 491, 492, Senior Honors Projects
· Elec 590, 599, Graduate Independent Projects
Ph.D. May 2004, “Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation”
M.S. May 2000, “Baseband Architecture Design for Future Wireless Base-Station Receivers”
Current Address: sridhar.rajagopal@wiquest.com, WiQuest, Inc., Allen, TX
Ph.D. January 2002, “Derivation and Application of Nonlinear Analytical Redundancy Techniques with Applications to Robotics” (co-supervised with I. D. Walker).
M.S. May 1997, “Fault Tolerance in Robot Systems.”
Current Address: mleuschen@nomadics.com, Nomadics, Inc., Stillwater, OK
Ph.D. September 2000, “Multiuser Information Processing in Wireless Communication”
M.S. May 1997, “Detection Algorithms for CDMA Systems.”
Current Address: sumand@bell-labs.com, Lucent, Bell Labs, Murray Hill, NJ.
Honored by MIT Technology Review in Top 100 Young Innovators of 2004
Ph.D. December 1998, “Algorithms and Architectures for Channel Estimation in Wireless CDMA Communication Systems,”
M.S. May 1995, “An Integrated CAD Framework Linking VLSI Layout Editors & Process Simulators.”
Current Address: chaitali@ti.com, Texas Instruments, Dallas, TX.
Ph.D. May 1996, “Parallel Algorithms and Architectures for Near-Far Resistant CDMA Acquisition.”
M.S. May 1991, “Architectural, Numerical and Implementation Issues in the VLSI Design of an Integrated CORDIC-SVD Processor.”
Current Address: kkota@cicada-semi.com, Cicada Semiconductor Corporation, Austin, TX.
Ph.D. May 1994, “Dynamic Fault Detection and Intelligent Fault Tolerance for Robotics,” (co-supervised with I. D. Walker)
M.S. December 1991, “Fault Detection and Fault Tolerance Methods for Robotics,” (co-supervised with I. D. Walker)
Current Address: mvisinsk@oss.oceaneering.com, Oceaneering Space Systems, Houston, TX.
Ph.D. May 1994, “Efficient VLSI Architectures for Matrix Factorizations.”
M.S. May 1991, “A Systolic VLSI Architecture for Complex SVD.”
Current Address: hemkumar@crystal.cirrus.com, Crystal Semiconductor Corp., Austin, TX.
M.S. May 2004 “Semi-Parallel Architectures For Real-time LDPC Coding”
M.S. May 2004 “Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures”
M.S. January 2003 “VITURBO: A Reconfigurable Architecture for Ubiquitous Wireless Networks”
Current Address: mani.vaya@cirrus.com, Cirrus Logic, Austin, TX.
M.S., January 2003“Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receiver.”
Current Address: vikram.chandrasekhar@ni.com, National Instruments, Austin, TX
M.S. May 2002,“Rapid Prototyping of Wireless Communications Systems”
Current Address: bryanj@clemson.edu, Clemson University, Clemson, SC.
M.S. May 2001, “A Reconfigurable Decoder Architecture for Wireless LAN and Cellular Systems”
Current Address: kanu@engim.com, Engim Inc., Acton, MA.
M.S. May 1999, “A Software Simulation Testbed for CDMA Wireless Communication Systems.”
Current Address: vishwas.sundaramurthy@nokia.com, Nokia Corporation, Irving, TX.
M.S. May 1999, “Implementation Issues of Multiuser Detection in CDMA Communication Systems.”
Current Address: gang.gary.xu@nokia.com, Nokia Corporation, Irving, TX.
Yuanbin Guo, (5th year Ph.D. student); Advanced Baseband Algorithms and Architectures for Interference Suppression in WCDMA and WLAN Systems (part-time at Nokia Research Center.),
Michael Brogioli,(5th year Ph.D. student); Reconfigurable and VLIW Style Architectures for Task Based Embedded Computing Workloads,
Marjan Karkooti(4th year Ph.D. student); Wireless Radio Testbed Architectures and LDPC Decoding,
Predrag Radosavljevic(4th year Ph.D. student); Wireless Radio Testbed Architectures and Application Specific Instruction Processors (ASIP),
Manik Gadhiok (2nd year M.S. student); VLSI System Design for ASIPS,
Frank Livingston, (4th year Ph.D. student); Power Efficient VLSI Multi-tier Network Interface Card Architectures (on leave).
Krishna Kiran Mukkavilli, Ph.D. (ECE) (Aazhang, Chair) 2003
Mohammad Jaber Borran, Ph.D. (ECE) (Aazhang) 2003
Liang Sun, Ph.D. (ECE) (Clark) 2003
Li Xu, Ph.D. (CS) (Cooper) 2003
Dinesh Rajan, Ph.D. (ECE) (Aazhang) 2002
Chu Xiang, Ph.D. (ECE) (Young) 2001
Srikrishna Bhashyam, Ph.D. (ECE) (Aazhang) 2001
Parthasarathy Ranganathan, Ph.D. (ECE) (Adve) 2000
Andrew Sendonaris, Ph.D. (ECE) (Aazhang) 1999
Yile Guo, Ph.D. (ECE) (Aazhang) 1999
Juan A. Rodriguez, Ph.D., (ECE) (Wilson) 1998
Raghavendra K. Madyastha, Ph.D., (ECE) (Aazhang) 1997
Deirdre L. Hamilton, Ph.D., (ECE) (Walker) 1996
Arati Deo, Ph.D., (ECE) (Walker) 1995
William Dawkins, Ph.D., (ECE) (Sinclair) 1993
Richard Murphey, Ph.D., (ECE) (Clark) 1991
Chris Steger, M.S., (ECE) (Aazhang, Chair) 2004
Nasir Ahmed, M.S., (ECE) (Aazhang) 2002
Mahsa Memarzadeh, M.S., (ECE) (Aazhang) 2001
Ahmad Khoshnevis, M.S., (ECE) (Aazhang) 2001
Ozgur Ertug, M.S., (ECE) (Varman) 2000
Krishna Kirin Mukavilli, M.S., (ECE) (Aazhang) 2000
Tarik Muharemovic, M.S., (ECE) (Aazhang) 2000
Damian Dobric, M.S., (ECE) (Bennett) 2000
Nadeem Ahmed, M.S., (ECE) (Baraniuk) 2000
Chu Xiang, M.S., (ECE) (Young) 1999
Dinesh Rajan, M.S., (ECE) (Aazhang) 1999
Yile Guo, M.S., (ECE) (Young) 1996
David Chung, M.S., (ECE) (Clark) 1996
Andrew Sendonaris, M.S., (ECE) (Aazhang) 1995
Michael G. McMahon, M.S., (ECE) (Clark) 1995
Stephen E. Bensley, M.S., (ECE) (Aazhang) 1994
Juan A. Rodriguez, M.S., (ECE) (Wilson) 1994
Jai Tang, M.S., (ECE) (Varman-Sinclair) 1993
Jay Greenwood, M.S., (ECE) (Bennett) 1992
Deirdre Hamilton, M.S., (ECE) (Bennett-Walker) 1992
Samir Khushalani, M.S., (ECE) (Clark) 1992
Ping Tian, M.S., (ECE) (Clark) 1992
Arati Deo, M.S., (ECE) (Walker) 1991
Vinay Pai, M.S., (ECE) (Varman) 1991
William Dawkins, M.S., (ECE) (Sinclair) 1990
· Judge, Rice Undergraduate Research Symposium, 2003.
· Faculty Contact, Undergraduate Recruiting, 2003-2003.
· Member of University Committee on Undergraduate Admissions, 1997-1999.
· Member of Faculty Council, 1991-1992.
Chair of Elections Committee
Member of Tenure and Ethics Committee.
· Engineering Divisional Advisor, Lovett Residential College, 1990-1996.
· Member of University Committee on Undergraduate Teaching, 1990-1991.
· Faculty Associate, Lovett Residential College, 1989-1999.
Outstanding Associate, 1990-1991, 1991-1992, 1992-1993, 1993-1994, 1994-1995.
· Member of Computer and Information Technology Institute, 1989-Present.
· ECE/CS Computer Systems Lab, Member, 2000-Present.
· Affiliates Committee, Chair, 1999-Present.
· Associate Director, Center for Multimedia Communications, 1999-Present.
· Member of Faculty Search Committee, 1999, 2002-2003.
· Member of Computer Committee, 1998-1999.
· Member of Graduate Committee, 1997-Present, 1988-1992.
· Chair of Computer Engineering Area Committee, 1997-1998.
· Member of Corporate Affiliates Committee, 1995-1996.
· Member of Curriculum Committee, 1994-1995.
· Member of Undergraduate Committee, 1994-1996.
· Chair of Library Committee, 1992-1994.
· IEEE Rice University Student Branch Advisor, 1990-1994.
· Chair of Safety Committee, 1990-1991.
· Member of Space Committee, 1989-1990.
· Mentor, Alliance for Graduate Education and the Professoriate (AGEP), Summer 2000.
· Faculty Mentor Program, Spring Independent School District, Spring, TX, 1990.
1999 - Present, IEEE Transactions on Robotics and Automation;
1994 - Present, Journal of VLSI Signal Processing;
1993 - Present, Journal of Computers and Electrical Engineering;
1993 - Present, Journal of Intelligent and Robotic Systems;
1993 - Present, Society for Computer Simulation Simulation Journal;
1993 - Present, IEEE Transactions on Parallel and Distributed Systems;
1993 - Present, IEEE Transactions on VLSI Systems.
1992 - Present, Journal of Robotics and Computer Integrated Manufacturing;
1992, IEEE Signal Processing Magazine;
1991 - Present, IEEE Computer Magazine;
1990, Parallel Computing Journal;
1990 - Present, Kluwer Academic Press;
1989 - Present, IEEE Transactions on Signal Processing;
1989 - Present, SIAM Journal on Matrix Analysis and Applications;
1987 - Present, Journal of Parallel and Distributed Computing;
1986 - Present, IEEE Transactions on Computers.
2002, IEEE International Symposium on Spread Spectrum Techniques and Applications; 1997, IEEE International Conference on Computer Design; 1993 - Present, International Conference on Application-Specific Array Processors; 1990 - Present, International Conference on Parallel Processing; 1989, HICSS23 - 23rd Hawaii International Conference on System Sciences; 1986 - Present, IEEE Symposia on Computer Arithmetic.
2003, Committee of Visitors, C-CR Division, CISE, National Science Foundation,
2003, Review Panelist, EIA Division, CISE, National Science Foundation,
2002, Mail Reviewer, C-CR Division, CISE, National Science Foundation,
2002, Review Panelist, C-CR Division, CISE, National Science Foundation,
2001, Site Review Panelist, EIA Division, CISE, National Science Foundation,
2000, Committee of Visitors, C-CR Division, CISE, National Science Foundation,
2000, Review Panelist, EHR Directorate, National Science Foundation,
2000, Reviewer, U.S. Civilian Research and Development Foundation,
2000, Mail Reviewer, INT Division, National Science Foundation,
1999, Review Panelist, EIA Division, CISE, National Science Foundation,
1999, Review Panelist, C-CR Division, CISE, National Science Foundation,
1998, Review Panelist, EIA Division, CISE, National Science Foundation,
1994, 1996, Review Panelist, DMII Division, ENG, National Science Foundation,
1989 - Present, Mail Reviewer, MIPS and C-CR Division, CISE, National Science Foundation.
1999-2000, Ph.D. thesis committee, Royal Institute of Technology, (KTH) Stockholm, Sweden.
1994, Ph.D. thesis committee, Indian Institute of Technology, Kharagpur.
§ Guest Editor, 2005 Special Issue on Application-specific Systems, Architectures and Processors, Journal of VLSI Signal Processing Systems, (with L. Thiele, S. Rajopadhye, and T. Noll).
§ Program Committee, 2005 IEEE International Conference on Communications (ICC), Seoul, Korea.
§ Program Committee, 2005 IEEE Microelectronics Systems Education Conf., Anaheim, CA.
§ Co-Chair, Signal Processing for Communications Symposium, 2004 IEEE Global Communications Conference (GLOBECOM), Dallas, TX.
§ General Co-Chair, 2004 IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Galveston, TX.
§ Invited Session Organizer, “VLSI Architectures and Implementations for Wireless Systems” 2004 38th Asilomar Conference on Signal, Systems, and Computers, Pacific Grove, CA.
§ Program Committee, 2004 IEEE Signal Processing Systems Conference (SIPS), Austin, TX.
§ Co-Chair, Program Committee, 2003 IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP), The Hague, The Netherlands.
§ Program Committee, 2003 IEEE Microelectronic Systems Education Conf., Anaheim, CA.
§ Chair, IEEE Computer Society Technical Committee on VLSI, 2002-2004.
§ Area Editor, Hardware and Architecture, Encyclopedia of Computer Science and Engineering, Wiley Interscience, 2002-2003 Edition.
§ Member, IEEE Transactions on VLSI, Editor-in-Chief Search Committee, 2002.
§ Program Committee, 2002 IEEE 13th International Conference on Application-specific Systems, Architectures and Processors, San Jose, CA.
§ Program Committee, 2001 IEEE Microelectronic Systems Education Conf., Las Vegas, NV.
§ Session Organizer, 2001 Texas Instruments DSP Fest, Wireless Applications, Houston, TX.
§ Session Chair, 2000 IEEE 12th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Boston, MA.
§ Session Chair, 1999 33rd Asilomar Conference on Signal, Systems, and Computers, Pacific Grove, CA.
§ Program Committee, 1999 IEEE 14th Symposium on Computer Arithmetic, Adelaide, Australia.
§ Program Committee, 1999 IEEE Microelectronic Systems Education Conference.
§ Program Committee, 1998 SPIE Symposium on Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, San Diego, CA.
§ Program Committee, 1997 IEEE International Conference on Computer Design, Austin, TX.
§ Program Committee and Publicity Chair, 1997 IEEE 13th Symposium on Computer Arithmetic, Asilomar, CA.
§ Publicity Chair, 1996 IEEE International Conference on Neural Networks, Washington, DC.
§ Guest Editor, 1995 Special Issue on Safety of Robotics Systems, Reliability Engineering and System Safety, (with I. D. Walker and K. E. Petersen).
§ Program Committee, 1995 IEEE 12th Symposium on Computer Arithmetic, Bath, UK.
§ Session Chair, 1995 IEEE 12th Symposium on Computer Arithmetic, Bath, UK.
§ Program Committee, 1994 International Symposium on Robotics and Manufacturing, Maui, HI.
§ Guest Co-Organizer, 1994 Special Issue on Fault Tolerance in Robotics, Journal of Computers and Electrical Engineering, (with I. D. Walker and M. Jamshidi).
§ Program Committee and Session Chair, 1992 SCS International Simulation Technology Conference, Clear Lake, TX.
§ Invited Session Co-Organizer, 1992 International Symposium on Robotics and Manufacturing, Sante Fe, NM, (with I. D. Walker).
§ Session Chair, 1991 SIAM Conference on Parallel Processing for Scientific Computing, Houston, TX.
§ Chair, IEEE Houston Section Circuits and Systems Society, 1990-Present.
· 2001, Hewlett Packard, Fort Collins, CO.
· 1995-, Nokia Corporation, Irving, TX and Helsinki, Finland.
· 1994, Baker & Botts, L.L.P., Patent Review, Austin, TX.
· 1990, Compaq Computer Corporation, Houston, TX.
· Association for Computing Machinery
· Institute of Electrical and Electronics Engineers
· Society for Industrial and Applied Mathematics
· Society of Photo-Optical Instrumentation Engineers
1. V. Chandrasekhar, F. Livingston, J. R. Cavallaro, Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers. International Journal of Embedded Systems, (Accepted, August 2004).
2. M. L. Leuschen, I. D. Walker, J. R. Cavallaro, “Fault Residual Generation via Nonlinear Analytical Redundancy,” IEEE Transactions on Control Systems Technology, (Accepted, April 2004).
3. S. Das, E. Erkip, J. R. Cavallaro, B. Aazhang, “Low Complexity Iterative Multiuser Detection and Decoding for Real-Time Applications,” IEEE Transactions on Wireless Communications, (Revised, July 2004).
In Preparation:
4. S. Rajagopal, J. R. Cavallaro, “Truncated On-line Arithmetic with Applications to Communication Systems,” IEEE Transactions on Computers, (In preparation, August 2004).
5. S. Rajagopal, J. R. Cavallaro, S. Rixner, “Design Space Exploration for Real-Time Embedded Stream Processors,” IEEE Micro, pp. 54-66, Volume 24, No. 4, (July-August 2004).
6. B. Jones, J. R. Cavallaro, A Rapid Prototyping Environment for Wireless Communication Embedded Systems, EURASIP Journal on Applied Signal Processing, Special Issue on: Rapid Prototyping of DSP Systems, pp. 603-614, Volume 2003, No. 6, (May 2003).
7. J. R. Cavallaro, Architectures for Heterogeneous Multi-Tier Networks, Kluwer Journal on Wireless Personal Communications, pp. 285-296, Volume 22, No. 2, (August 2002).
8. S. Rajagopal, S. Bhashyam, J. R. Cavallaro, B. Aazhang, “Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers,” IEEE Transactions on Wireless Communications, pp. 468-479, Volume 1, No. 3, (July 2002).
9. S. Rajagopal, S. Bhashyam, J.R. Cavallaro, and B. Aazhang, “Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-station Receivers”, Journal of VLSI Signal Processing: special issue on ASAP, pp. 143-156, Volume 31, No. 2, (June 2002).
10. G. Xu, S. Rajagopal, J. R. Cavallaro, and B. Aazhang, “VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers”, Journal of VLSI Signal Processing: special issue on signal processing for wireless communications: algorithms, performance and architecture, pp. 21-33, Volume 30, No. 1-3, (March 2002).
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