We are now going to build the mask layout view of our cmos inverter.
Since we intend
to use these standard cells with the automatic place and route, it is
important to remember that vias must be at the intersections of the routing grid.
If you have not already, please familiarize yourself with the routing grid here. For your first layout we will give you the coordinates of the design, but for future standard cells it might be helpful to build a the routing grid using text rectangles to guide the layout process.
To create a cell named "inv" in your new library,
First select File -> New -> Cellview ... from either the library manager or CIW windows.
A Create New File form pops up.
Enter the name of your local library as Library Name; enter "inv" as Cell Name, "layout" as View Name; select "Virtuoso"
for Tool then click "OK".
Cell "inv" with "layout" view will be opened in your library for you to edit.
Two more windows will be brought up. The first one is
Layer Select Window (LSW).
The second one is Virtuoso Editing window.
Another useful feature of the LSW are the AV NV AS NS buttons. These buttons speficy which layers in the layout window can be viewed or selected.
Window -> Zoom has a few options for zooming, but you may find the following shortcuts useful. To zoom out, type shift-z, to zoom in type control-z or click and drag with your right mouse button to zoom to the area under the rectangle created by dragging. Be careful with the last option, a single right click repeats the last command).
Use the bind key k to bring up the ruler command. left click on two points to draw a ruler on the design (measures in microns). This is a handy
in determining whether or not you are following the spacing rules.
Drawing a rectangle
The most common shape in a layout is rectangle. To draw rectangles
Another useful shape is the polygon. To draw a polygon
Paths are easy ways to route metal layers. To create a path
If you are using the 0.5 micron technology, make sure that lambda is 0.15
(actually, lambda is .3 microns, but the routing resolution is 1/2 lambda).
To do so follow the following proceedure once you have opened a layout window.
In the layout window, click on Options -> Display
A Display options window pops up.
Change the "X snap spacing" &
"Y snap spacing" to 0.15.
Click on OK.
Start building the Inverter
Finally we are going to build
a PMOS transistor and a NMOS transistor by drawing rectangles, polygons, and paths in various
layers. Notice that we are using scalable Nwell submicron technology and
the layers below are layers with drawing purpose. The numbers refer to the coordinates of your mouse (X,Y), displayed in the upper left-hand portion of the screen. Please draw every shape with care.
Layer | first corner | second corner |
---|---|---|
pselect dg | (0.00, 10.50) | (4.80, 16.80) |
nselect dg | (0.00, 1.20) | (4.80, 5.40) |
active dg | (0.60, 11.10) | (4.20, 16.20) |
active dg | (0.60, 1.80) | (4.20, 3.90) |
nwell dg | (-2.40, 7.20) | (7.80, 19.80) |
Layer | first point | second point | third point | fourth point | fifth point | sixth point | seventh point | eighth point |
---|---|---|---|---|---|---|---|---|
poly dg | (2.10, 1.50) | (2.70, 1.50) | (2.70, 16.80) | (2.10, 16.80) | (2.10, 6.90) | (0.60, 6.90) | (0.60, 5.70) | (2.10, 5.70) |
Save you Design:
It is good practice to save your design every few minutes to prevent loss
of your design in case cadence crashes on you.
To save your design
Click on Design -> Save.
Now you have drawn the diffusions and a poly contact for gate. You are
ready to put down the metal contact for the sources and drains. For this
we will use pre-defined contacts. In the Layout Editing Window type i
for the instance bind key (or Create -> Instance in the pull-down menus)
Now browse to find cell m1_n in the library you created. This
contact is simply a 0.6u square of layer cc surrounded by two 1.2u squares
of metal1 and active, enclosed by a 2.4 square of nselect. Left-click at
(0.9, 2.1) to place the first instance and (3.3, 2.4) to place the second. To expand the view of the instance, type Shift-F (Control - f toggles back to unexpanded view).
Now change from m1_n to m1_p to place the source contacts. The
Only difference between the m1_n and m1_p contacts is that nselect is replaced
with pselect. The m1_p contacts should be placed at (0.9, 12.3), (0.9, 13.8),
(0.9, 15.3), (3.3, 12.3), (3.3, 13.8), and (3.3, 15.3).
Now to add a few metal1 connections.
layer | first corner | second corner |
---|---|---|
metal1 dg | (0.60, 13.20) | (1.80, 17.10) |
metal1 dg | (3.00, 11.70) | (4.20, 15.90) |
metal1 dg | (0.60, 0.90) | (1.80, 3.00) |
layer | first point | last point |
---|---|---|
metal1 dg | (3.60, 2.10) | (3.60, 15.90) |
metal1 dg | (1.20, 12.00) | (1.20, 14.10) |
The contacts on the drain of PMOS are now connected to the contacts on the
drain of the NMOS. To make this inverter work, we need power supplies. The ntap
and ptap instances provide substrate contacts for the design.
layer | first corner | second corner |
---|---|---|
metal1 dg | (-0.60,17.10) | (5.40,18.90) |
metal1 dg | (-0.60,-0.90) | (5.40, 0.90) |
Instance | first contact | second contact |
---|---|---|
ptap | (-0.30, -0.30) | (4.50, -0.30) |
ntap | (-0.30, 17.70) | (4.50, 17.70) |
Okay, we can now draw the input and output pins. Begin by placing an m1_poly instance (poly to metal1 contact, uses poly instead of active and no select rectangle) at (0.90, 6.00), a metal1 dg rectangle at (0.6, 5.1), (1.8, 5.7), and a metal1 dg path from (1.2, 4.5) to (1.2, 7.5).
It looks like the inverter layout has been finished. But in order to let the router know how to connect this cell to others, pins are needed for inputs, outputs, and power supply nodes. Pins define where the wires outside the cell can be connected to the cell. The input pin will be a, the output pin will be y, power is called vdd! and ground gnd!. Before placing the pin, it is a good idea to get into the habit of placing metal rectangles in the appropriate layer. This becomes more important in hierarchical designs when the metal over which the pin is being created might only exist in a subcell, and not on the current level.
layer | first corner | second corner |
---|---|---|
metal1 dg | (0.75, 4.05) | (1.65, 4.95) |
metal1 dg | (0.75, 7.05) | (1.65, 7.95) |
metal1 dg | (3.15, 4.05) | (4.05, 4.95) |
metal1 dg | (3.15, 7.05) | (4.05, 7.95) |
metal1 dg | (3.15,10.05) | (4.05,10.95) |
Comment: You might get Create Shape Pin form in the first
place.
Comment: Bind key for Create Pin is "^p" which means
"Control-p".
Comment: "vdd!" and "gnd!" are names reserved for power
pins. Don't use these names for other purposes.
The next image shows the routing grid for the inverter to give you a better idea of how the pins are placed along the intersectionsof the cell routing grid. As you can see, the origin of the cell (0.00,0.00) is located in the lower left-hand corner, at the edge of the bounding box (this should be the case for all of your standard cells).
You've just finished you first layout using ami06 technology. You can
finish this tutorial by exiting. Select
Window -> Close to exit layout editor, then in
CIW select Open -> Quit to quit Cadence.
Refer to 'Virtuoso Layout Editor User Guide' for more information about layout editor.