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VLSI Signal Processing Research at Rice University |
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VLSI Signal Processing Research at Rice University |
The VLSI Signal Processing for Communications Group is presently involved in a number of projects to improve the real-time performance of parallel algorithms for wireless communication systems. The results of these projects are important for the development of the next generation of cellular mobile telephones. Support for this work has been provided by the National Science Foundation, the State of Texas, National Instruments, Texas Instruments, and Nokia Corporation.
Previous work in the group has been in the area of special-purpose architectures for matrix factorizations, including the Singular Value Decomposition (SVD). Computer arithmetic algorithms and their VLSI realizations, especially the CORDIC (Coordinate Rotation Digital Computer) algorithms, have been applied to the SVD. Applications of these architectures have included the inverse kinematics problem for the control of redundant robot manipulators.
Faculty
Laboratory - Rice CMC Laboratory
Current Graduate Students
Yuanbin Guo, (Ph.D. student); Advanced Baseband Algorithms and Architectures for Interference Suppression in WCDMA and WLAN Systems (part-time at Nokia Research Center.),
Michael Brogioli, (Ph.D. student); Reconfigurable and VLIW Style Architectures for Task Based Embedded Computing Workloads,
Marjan Karkooti (Ph.D. student); Wireless Radio Testbed Architectures and LDPC Decoding,
Predrag Radosavljevic (Ph.D. student); Wireless Radio Testbed Architectures and Application Specific Instruction Processors (ASIP),
Manik Gadhiok (M.S. student); VLSI System Design for ASIPS,
Sridhar Rajagopal Ph.D. May 2004, “Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation” M.S. May 2000, “Baseband Architecture Design for Future Wireless Base-Station Receivers”Current Address: sridhar.rajagopal@wiquest.com, WiQuest, Inc., Allen, TX
Martin Leuschen Ph.D. January 2002, “Derivation and Application of Nonlinear Analytical Redundancy Techniques with Applications to Robotics” (co-supervised with I. D. Walker). M.S. May 1997, “Fault Tolerance in Robot Systems.” Current Address: mleuschen@nomadics.com, Nomadics, Inc., Stillwater, OK
Suman Das Ph.D. September 2000, “Multiuser Information Processing in Wireless Communication” M.S. May 1997, “Detection Algorithms for CDMA Systems.” Current Address: sumand@bell-labs.com, Lucent, Bell Labs, Murray Hill, NJ.
Chaitali Sengupta, Honored by MIT Technology Review in Top 100 Young Innovators of 2004 Ph.D. December 1998, “Algorithms and Architectures for Channel Estimation in Wireless CDMA Communication Systems,” M.S. May 1995, “An Integrated CAD Framework Linking VLSI Layout Editors & Process Simulators.” Current Address: chaitali@ti.com, Texas Instruments, Dallas, TX.
Kishore Kota Ph.D. May 1996, “Parallel Algorithms and Architectures for Near-Far Resistant CDMA Acquisition.” M.S. May 1991, “Architectural, Numerical and Implementation Issues in the VLSI Design of an Integrated CORDIC-SVD Processor.” Current Address: kkota@cicada-semi.com, Cicada Semiconductor Corporation, Austin, TX.
Monica L. Visinsky Ph.D. May 1994, “Dynamic Fault Detection and Intelligent Fault Tolerance for Robotics,” (co-supervised with I. D. Walker) M.S. December 1991, “Fault Detection and Fault Tolerance Methods for Robotics,” (co-supervised with I. D. Walker) Current Address: mvisinsk@oss.oceaneering.com, Oceaneering Space Systems, Houston, TX.
Nariankadu D. Hemkumar Ph.D. May 1994, “Efficient VLSI Architectures for Matrix Factorizations.” M.S. May 1991, “A Systolic VLSI Architecture for Complex SVD.” Current Address: hemkumar@crystal.cirrus.com, Crystal Semiconductor Corp., Austin, TX.
Marjan Karkooti M.S. May 2004, “Semi-Parallel Architectures For Real-time LDPC Coding”
Predrag Radosavljevic M.S. May 2004, “Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures”
Mani Vaya, M.S. January 2003, “VITURBO: A Reconfigurable Architecture for Ubiquitous Wireless Networks” Current Address: mani.vaya@cirrus.com, Cirrus Logic, Austin, TX.
Vikram Chandrasekhar M.S., January 2003, “Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receiver.” Current Address: vikram.chandrasekhar@ni.com, National Instruments, Austin, TX
Bryan Jones M.S. May 2002, “Rapid Prototyping of Wireless Communications Systems” Current Address: bryanj@clemson.edu, Clemson University, Clemson, SC.
Kanu Chadha M.S. May 2001, “A Reconfigurable Decoder Architecture for Wireless LAN and Cellular Systems” Current Address: kanu@engim.com, Engim Inc., Acton, MA.
Vishwas Sundaramurthy M.S. May 1999, “A Software Simulation Testbed for CDMA Wireless Communication Systems.” Current Address: vishwas.sundaramurthy@nokia.com, Nokia Corporation, Irving, TX.
Gang Xu M.S. May 1999, “Implementation Issues of Multiuser Detection in CDMA Communication Systems.” Current Address: gang.gary.xu@nokia.com, Nokia Corporation, Irving, TX.
Publications Papers, technical reports and bibliographies via the CMC Database.