|
Topic
|
Speaker & Affiliation
|
|
New devices and architectures
Fault-tolerant and reconfigurable nano-systems
|
Ramesh Karri
Polytechnic University
|
|
Hardware/software co-design
High-level synthesis and optimization
System-level design
|
Ahmed Jerraya
TIMA Laboratory, France
|
|
Logic synthesis and optimization
|
Andreas
Kuehlmann
Cadence Berkeley
Labs
|
|
Circuit and interconnect modeling and design
Signal integrity issues
Timing and statistical timing analysis
|
Massoud Pedram
University of Southern California
|
|
Place and route
Floor-planning
Physical design
|
Jason Cong
University
of California, Los
Angeles
|
|
Design for manufacturing
|
Andrew Kahng
University
of California, San
Diego
|
|
Verification and validation
|
Bruce Wile
IBM
|
|
Low power design
Power and leakage in new devices
|
Vijaykrishnan
Narayanan
Penn. State
University
|
|
Analog, RF and mixed-signal design automation
|
Jaijeet Roychowdhury
University
of Minnesota
|
|
Testing
|
Shawn
Blanton
Carnegie Mellon
University
|
