ELEC 523 & COMP 523: Computer-Aided Design for VLSI

This course focuses on key topics in Computer-Aided Design for VLSI - functional verification, logic synthesis and technology mapping, logic simulation, physical design, testing - that I will introduce and discuss in depth. A substantial project (40% credit) is expected of students who register. There is NO required text for the course. The course material will be based upon the lectures and handouts in class. For the most part, the course is self-contained and should be accessible to anyone with the prerequisites.

Tentative topics and outline

• Algorithms and data structures - This will involve a review of the basics of algorithms and data structures, object-oriented programming, generic programming, and the C++ standard template library (STL).

• Functional verification - The basics of synthesis and verification will be discussed. A possible assignment will introduce combinational/sequential equivalence checking using binary decision diagrams (BDDs), isomorphism, hashing, etc.

• Logic synthesis and technology mapping - The basics of logic synthesis, timing analysis and optimization, and technology mapping will be discussed. A possible assignment will focus on structural technology mapping of a normalized (or canonical) circuit to a prescribed library of cells using dynamic programming techniques.

• Logic simulation and testing - The basics of logic and fault simulation and automatic test pattern generation (ATPG) will be discussed. A possible assignment will involve building an efficient logic simulator.

Class Notes and Papers

References

• The C++ Standard Library: A Tutorial and Reference by Nicolai M. Josuttis
  
• C++ Templates: The Complete Guide by David Vandevoorde and Nicolai M. Josuttis
  
• Logic Synthesis and Verification edited by Soha Hassoun, Tsutomu Sasao, and Robert K. Brayton
  
• Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits by Michael L. Bushnell and Vishwani D. Agrawal
  
• Algorithms for VLSI Design Automation by Sabih H. Gerez
  
• Algorithms for VLSI Physical Design Automation by Naveed A. Sherwani
  

Format & Evaluation: 1-2 homeworks will be assigned over the course of the semester. Homework will be graded and will be worth a total of 20 pts. Three take-home tests will be worth a total of 40 points (10, 15, 15). There will be one semester-long project worth 40 pts for a total of 100 points.

Homework, tests, and solutions from previous offerings of this course are off limits, under the honor code.

Where does this course fit in? This course is intended as a broad introduction to the topic of computer-aided design for VLSI.

University disability accommodation policy: Any student with a documented disability needing academic adjustments or accommodations is requested to speak with the course instructor during the first two weeks of class. All discussions will remain confidential. Students with disabilities should also contact Disabled Student Services in the Ley Student Center.