Laboratory for Sub-100nm Design

2010

Xuebei Yang, Masoud Rostami, and Kartik Mohanram, "Graphene polarity controllable amplifier and its applications," (under review) Design Automation Conference, 2010.
Xuebei Yang, Jyotsna Chauhan, Jing Guo, and Kartik Mohanram, "Technology exploration for graphene tunneling FETs," (under review) Design Automation Conference, 2010.
Masoud Rostami and Kartik Mohanram, "Statistical Vth swapping and gate sizing based on sensitivity analysis," (under review) Design Automation Conference, 2010.
Mihir Choudhury, Masoud Rostami, and Kartik Mohanram, "Dominant critical gate identification using geometric programming," (under review) European Test Symposium, 2010.
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, and Robert Aitken, "TIMBER: Time borrowing and error relaying for online timing error resilience," (to appear) Design Automation and Test in Europe, 2010.
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, and Robert Aitken, "Accurate analytical model for performance degradation due to gate oxide breakdown in combinational logic," (to appear) Design Automation and Test in Europe, 2010.
Haykel ben Jamaa, Kartik Mohanram, and Giovanni de Micheli, "Power consumption of logic circuits in ambipolar carbon nanotube technology," (to appear) Design Automation and Test in Europe, 2010.
Masoud Rostami and Kartik Mohanram, "Novel dual-Vth independent-gate FinFET circuits," Asia and South Pacific Design Automation Conference, 2010.

2009

Mihir Choudhury and Kartik Mohanram, "Timing-driven optimization using lookahead logic circuits,'' Design Automation Conference, 2009.
Abhishek Garg, Kartik Mohanram, Alessandro Di Cara, Ioannis Xenarios, and Giovanni De Micheli, "Modeling stochasticity and robustness in gene regulatory networks," Bioinformatics (and the International Conference on Intelligent Systems for Molecular Biology), 2009.
Haykel ben Jamaa, Kartik Mohanram, and Giovanni de Micheli, "Logic circuits with ambipolar CNTFETs: Novel opportunities for multi-level logic synthesis,'' Design Automation and Test in Europe, 2009.
Mihir Choudhury and Kartik Mohanram, "Masking timing errors on speed-paths in logic circuits,'' Design Automation and Test in Europe, 2009.
Mihir Choudhury, Quming Zhou, and Kartik Mohanram, "Soft error rate reduction using circuit optimization and transient filter insertion," Journal of Electronic Testing, 2009.
Mihir Choudhury and Kartik Mohanram, "Reliability analysis of logic circuits,'' IEEE Trans. Computer-aided Design of Integrated Circuits and Systems, Vol. 28, No. 3, pp. 392-405, Mar. 2009.

2008

Kartik Mohanram and Jing Guo, "Graphene nanoribbon FETs: Technology exploration and CAD,'' Proc. Intl. Conference Computer-aided Design, 2008.
Pei Zhao, Mihir Choudhury, Kartik Mohanram, and Jing Guo, "Computational model of edge effects in graphene nanoribbon transistors,'' Nano Research, Nov. 2009.
Pei Zhao, Mihir Choudhury, Kartik Mohanram, and Jing Guo, "Analytical theory of graphene nanoribbon transistors,'' Proc. Intl. Workshop on Design and Test of Nano Devices, Circuits and Systems, 2008.
Yehia Massoud, Sami Kirolos, and Kartik Mohanram, "Analytical model-based technique for efficient evaluation of noise robustness considering parameter variations", Analog Integrated Circuits and Signal Processing, 2008.
Mihir Choudhury, Youngki Yoon, Jing Guo, and Kartik Mohanram, "Technology exploration for graphene nanoribbon FETs,'' Proc. Design Automation Conference, 2008.
Quming Zhou, Mihir Choudhury, and Kartik Mohanram, "Tunable transient filters for soft error rate reduction in combinational circuits," Proc. European Test Symposium, 2008.
Mihir Choudhury and Kartik Mohanram, "Approximate logic circuits for low overhead, non-intrusive concurrent error detection," Proc. Design Automation and Test in Europe, 2008.

2007

Kai Sun, Quming Zhou, Kartik Mohanram, and Danny C. Sorensen, "Parallel domain decomposition for simulation of large-scale power grids", Proc. Intl. Conference Computer-aided Design, 2007.
Quming Zhou, Lin Zhong, and Kartik Mohanram, "Power signal processing: A new perspective for power analysis and optimization", Proc. Intl. Symposium on Low Power Electronic Design, 2007.
Sami Kirolos, Kartik Mohanram, and Yehia Massoud, "A model-based technique for efficient evaluation of noise robustness", Proc. Intl. Midwest Symposium on Circuits and Systems, 2007.
Mosin Mondal, Kartik Mohanram, and Yehia Massoud, "Parameter-variation-aware analysis for noise robustness", Proc. Intl. Symposium on Quality Electronic Design, pp. 655-659, 2007.
Mihir Choudhury and Kartik Mohanram, ''Accurate and scalable reliability analysis of logic circuits,'' Proc. Design Automation and Test in Europe, pp. 1454-1459, 2007.
Mihir Choudhury, Kyle Ringgenberg, Scott Rixner, and Kartik Mohanram, ''Single-ended coding techniques for off-chip interconnects to commodity memory,'' Proc. Design Automation and Test in Europe, pp. 1072-1077, 2007.

2006

Mihir Choudhury, Quming Zhou, and Kartik Mohanram, ''Design optimization for single-event upset robustness using simultaneous dual-V_DD and sizing techniques,'' Proc. Intl. Conference on Computer-aided Design, pp.204-209, 2006.
Alan L. Cox, Kartik Mohanram, and Scott Rixner, ''Dependable ≠ Unaffordable,'' Workshop on Architectural and System Support for Improving Software Dependability, 2006.
Quming Zhou and Kartik Mohanram, ''Elmore model for energy estimation in RC trees,'' Proc. Design Automation Conference, pp. 965-970, 2006.
Quming Zhou, Mihir Choudhury, and Kartik Mohanram, ''Design optimization for robustness to single-event upsets,'' Proc. VLSI Test Symposium, pp. 202-207, 2006.
Quming Zhou, Kai Sun, Kartik Mohanram, and Danny C. Sorensen, ''Large power grid analysis using domain decomposition,'' Proc. Design Automation and Test in Europe, pp. 27-32, 2006.
Quming Zhou and Kartik Mohanram, ''Gate sizing to radiation harden combinational logic,'' IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Vol. 25, No. 1, pp. 155-166, Jan. 2006.

2005

Kartik Mohanram and Scott Rixner, ''Context-independent codes for off-chip interconnects,'' Lecture Notes in Computer Science, vol. 3471, pp. 107-119, Dec. 2005.
Kartik Mohanram, '' Simulation of transients caused by single-event upsets in combinational logic,'' Proc. International Test Conference, pp. 1-9, 2005.
Quming Zhou, Kartik Mohanram, and Athanasios C. Antoulas, ''Structure preserving reduction of frequency dependent interconnect,'' Proc. Design Automation Conference, pp. 939-942, 2005.
Kartik Mohanram, ''Closed-form simulation and robustness models for SEU-tolerant design,'' Proc. VLSI Test Symposium, pp. 327-333, 2005.

2004

Quming Zhou and Kartik Mohanram, ''Cost-effective radiation hardening technique for combinational logic,'' Proc. Intl. Conference on Computer-aided Design, pp. 100-106, 2004.
Quming Zhou and Kartik Mohanram, '' Analysis of Delay Caused by Bridging Faults in RLC Interconnects,'' Proc. Intl. Test Conference, pp. 1044-1052, 2004.
Kartik Mohanram and Nur A. Touba, ''Lowering Power Consumption in Concurrent Checkers Via Input Ordering,'' IEEE Transactions on VLSI Systems, Vol. 12, No. 11, pp. 1234-1243, 2004.
Quming Zhou and Kartik Mohanram, ''Transistor Sizing for Radiation Hardening,'' Proc. Intl. Reliability Physics Symposium, pp. 310-315, 2004.

1998 to 2003

Kartik Mohanram and Nur A. Touba, ''Partial error masking to reduce soft error failure rate in logic circuits,'' Proc. Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 433-440, 2003.
Kartik Mohanram and Nur A. Touba, ''Cost-effective approach for reducing soft error failure rate in logic circuits,'' Proc. Intl. Test Conference, pp. 893-901, 2003.
Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, and Nur A. Touba, ''Synthesis of low-cost parity-based partially self-checking circuits,'' Proc. Intl. On-line Testing Symposium, pp. 35-40, 2003.
Kartik Mohanram and Nur A. Touba, ''Eliminating non-determinism during test of high-speed source synchronous differential buses,'' Proc. VLSI Test Symposium, pp. 121-127, 2003.
Kartik Mohanram and Nur A. Touba, ''Input ordering in concurrent checkers to reduce power consumption,'' Proc. Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 87-95, 2002.
Kartik Mohanram, C. V. Krishna, and Nur A. Touba, ''A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL,'' Proc. Intl. Symposium on Circuits and Systems, Vol. 1, pp. 577-580, 2002.
Jawahar Jain, Kartik Mohanram, Dinos Moundanos, Yuan Lu, and Ingo Wegener, ''Analysis of composition complexity and how to obtain smaller canonical graphs,'' Proc. Design Automation Conference, pp. 681-686, 2000.
''Probabilistic Verification of Boolean Functions and Partitioned-OBDDs,'' Dagstuhl Seminar (2000181) on Probabilistic Methods in Verification, 2000.
Abhijit Jas, Kartik Mohanram, and Nur A. Touba, ''An embedded core DFT scheme to obtain highly compressed test sets,'' Proc. Asian Test Symposium, pp. 275-280, 1999.

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