Marjan Karkooti

Biography:

I am a graduate student at Rice University in the CMC Group of the Electrical & Computer Engineering Department. My research area is Designing VLSI Architectures for Wireless Communications. My advisor is Prof. Joseph R. Cavallaro.

Education:

• PhD in Computer Engineering, Rice University, Houston , Texas (in progress).

• M.S. in Computer Engineering, Rice University, Houston , Texas, May 2004.

• M.S. in Socio-economic Systems Engineering, Institute for Research in Planning and Development , Tehran, Iran, Sep 2000.

• B.S. in Electrical and Control Systems Engineering, Sharif University of Technology, Tehran, Iran, Feb 1997.

Publications:

• M. Karkooti and J. R. Cavallaro,"Cooperative Communications Using Scalable, Medium Block-length LDPC Codes". IEEE Wireless communication and networking conference. WCNC 2008, Accepted.


• M. Karkooti and J. R. Cavallaro,"Distributed Decoding in Cooperative Communications". To appear in IEEE Forty-First Asilomar Conference on Signals, Systems, and Computers. Nov 2007.


• M. Karkooti, P. Radosavljevic, and J. R. Cavallaro,"Configurable LDPC Decoder Architectures for Regular and Irregular Codes". The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Submitted Jan 2007.


• Y. Sun, M. Karkooti and J. R. Cavallaro, "VLSI Decoder Architecture for High Throughput, Variable Block-Size and Multi-Rate LDPC Codes". IEEE International symposium on Circuits and Systems (ISCAS 2007), Accepted.


• P.Radosavljevic, M. Karkooti, A. de Baynast, and J. R. Cavallaro, “Tradeoff analysis and architecture design of high throughput irregular LDPC decoders,” IEEE Transactions on Circuits and Systems-I: Regular Papers (Submitted in October 2006).


• Y.Sun, M. Karkooti and J. R. Cavallaro, “High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems” Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software. Oct 2006, Dallas. [pdf]


• M. Karkooti, P. Radosavljevic, and J. R. Cavallaro, “Configurable high throughput irregular LDPC decoder architecture: tradeoff analysis and implementation,” to appear in the 17th IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), September 2006. [pdf]


• P.Radosavljevic, A. de Baynast, M. Karkooti, and J. R. Cavallaro, “Multi-rate high-throughput LDPC decoder: tradeoff analysis between decoding throughput and area,” to appear in the 17th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), September 2006. [pdf]


• P.Radosavljevic, A. de Baynast, M. Karkooti, and J. R. Cavallaro, “High-throughput multi-rate LDPC decoder based on architecture-oriented parity check matrices,” in the 14th European Signal Processing Conference (EUSIPCO), September 2006. [pdf]


• M. Karkooti, J. Cavallaro, C. Dick, FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm, IEEE Asilomar Conference on Signals, Systems, and Computers, November 2005. [pdf]
• M. Karkooti, Semi-Parallel Architectures For Real-time LDPC Coding, Masters Thesis, Houston, TX, May 2004. [pdf]


• M. Karkooti and J. Cavallaro, Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding, International Conference on Information Technology(ITCC), pp. 579-585, Volume 1, April 2004. [ps]

Last Modified : March 2007