Key challenges
Designing systems for these new workloads and appliances is motivated by
several considerations: (i) orders-of-magnitude higher computing requirements than what is currently available, (ii) greater emphasis on
metrics such as power consumption, cost, and reliability, and (iii) possibility of new architectural designs motivated by emerging technologies
that allow more transistors and greater on-chip system integration (e.g.,
memory, reconfigurable logic). All these trends open up a number of fundamental research areas in computer architecture that are both
intellectually satisfying and have high commercial value. Interesting
problems in processor and system design need to be solved at all levels of
the computing continuum:
(i) at the level of client (e.g., desktops, laptops, personal assistants,
internet-appliances)
(ii) at the level of the communication infrastructure (e.g., network
routers, communication processors)
(iii) at the level of the servers (e.g., enterprise data servers, web
servers).
My Research
My past and current research focuses on architectures for desktop
processors for media processing, handset and base station processors for
wireless communications, and processor and system design for database servers. I intend to continue on these research areas as well as expand my
focus to look at other parts of this computing continuum (e.g., internet-appliances, network routers). As in the past, I expect my work to
benefit significantly from collaboration with other industrial and academic
research groups (especially focusing on applications development in databases, artificial intelligence, human-computer interaction, networks,
signal processing, and communications).
Parthasarathy Ranganathan received his B.Tech degree from the Indian
Institute of Technology, Madras in 1994, and his M.S. degree from Rice University in 1997. He is currently a doctoral candidate at the
Department of Electrical and Computer Engineering at Rice University. His research interests are in
high-performance computer
architecture, parallel computing, and performance evaluation, with
specific focus on architectures for emerging applications and
techniques to use instruction-level parallelism. He is a primary
developer and maintainer of the publicly distributed Rice Simulator
for ILP Multiprocessors (RSIM) and a recipient of the Lodieska
Stockbridge Vaughan fellowship.
Click here for Partha Ranganathan's vitae.