Yuanbin Guo

Ph.D, Electrical and Computer Engineering

Rice University

Office:

Research Technology and Platform

Nokia Siemens Networks

6000 Connections Dr. Irving, TX, 75039

 

Home:

107 Pecan Valley Dr., Irving, TX, 75063

Mobile: 469-767-5681; Tel: 972-910-0712.

Email: ybguo_Nokia@yahoo.com

 

Research Interest

  • Wireless multimedia communication networks, sensor networks, CDMA, HSPA, OFDM, LTE, Femto home BTS
  • Equalization, detection and coding for multiple antenna/sensor systems, MIMO, space-time codes
  • Parallel algorithms and high-speed VLSI DSP architecture
  • Real-time embedded systems design and prototyping, System-on-Chip

 

Education

 

Thesis

·         PhD: Advanced MIMO-CDMA Receiver for Interference Suppression: Algorithms, System-on-Chip Architectures and Design Methodology, 2005.

          Advisor: Dr. Joseph R. Cavallaro, Professor of ECE and CS.

·         M. S.: UnixWare-based Intelligent Switching Platform: design and implementation, 1999.

          Advisor: Dr. Xixian Chen, director of Multimedia Communications Center, BUPT.

·         B. S.: Application of Spectral analysis in Active and Passive Digital Sonar Systems, 1996.

         Advisor: Professor Qihu Li, Former President, IOA, Academician, Chinese Academy of Sciences.

 

Professional Positions

 

  • 2007.4-present     Research Specialist, Research Technology and Platform, Nokia Siemens Networks, Irving, TX.
  • 2006.3-2007.4         Research Specialist, Strategy and Technology, Nokia Networks, Irving, TX.
  • 2006.1-2006.3         Senior Research Engineer, Nokia Networks Strategy and Technology, Irving, TX.
  • 2002-2005               Research Engineer, Wireless New Concept & Prototyping, Nokia Research, USA.
  • 2001                       Intern research engineer, Wireless Data Access Group, Nokia Research, USA,
  • 2000-2002               Research Assistant, Center for Multimedia Communications, Rice University.
  • 1999-2000               Member of Technical Staff1, Bell Labs, Lucent Technologies, China.
  • 1996-1999               Research Assistant, TI's Lab and Multimedia Communications Center, BUPT.
  • 1995-1996               Research Assistant, Signal Processing Labs, IOA, Chinese Academy of Sciences.

 

Academic Honors & Awards

  • 2004                        C-based EDA Design Expert Panelist, IEEE/ACM Design Automation Conference.
  • 2000                       Presidential Fellowship, Rice University.
  • 1999                        Appreciation of Contribution Award, Bell Labs, Lucent Technologies.
  • 1997-1998               Motorola Fellowship, 1st prize, BUPT, China.
  • 1996-1997               University Graduate Scholarship, 1st prize, BUPT, China.
  • 1997                        Excellency in Software Design, National College Computer Competition, China.
  • 1997                        2nd Prize in “Challenge-Cup” Sci-Tech & Software Design Competition, BUPT.
  • 1992-1995               Academic Excellency Scholarship, Peking University Scholarship, China.
  • 1994                        Excellent Paper Award, “Challenge-Cup” Young Scientist Competition, PKU.
  • 1991                        Ranked 6th in Hunan Province, National Exam for College Admissions, China.

 

Patents

  • P. Radosavljevic Y. Guo, J. R. Cavallaro, Methods and apparatus for iterative detection/decoding in MIMO-OFDM and SC-OFDMA systems using Bounded Soft Sphere Detection (BSSD), 2007.

 

 

  • Y. Guo, J. R. Cavallaro, System, apparatus, and method for adaptive weighted interference cancellation using Parallel Residue Compensation, Patent # (NOKM.114PA) filed on 25-Feb-05.

 

  • Y. Guo, D. McCain, J. R. Cavallaro, FFT-accelerated iterative MIMO chip equalizer for downlink CDMA receiver, Patent # (871.0141.U1.US), filed on 24-Nov-04.

 

  • Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, Reduced parallel and pipelined high order MIMO LMMSE receiver architecture, Patent # (871.0143.U1(US)) filed on 10-Dec-04.

 

  • Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, MIMO Kalman equalizer for CDMA wireless communication, Patent # (11/029900) filed on 04-Jan-05.

 

  • H. Nguyen, J. Zhang, Y. Guo, D. McCain, J. Dowling, Method and apparatus for downlink CDMA LMMSE equalization via weighted autocorrelation update, Patent # 873.0159.U1 (US), filed in 2004.

 

 

Professional Activities and Membership

  • Expert Panelist, IEEE DAC 2004, San Diego, CA, on-line video available on Mentor Graphics website.
  • Video interview and public talk video in  Design and Verification Conference on Demo-on-Demand website.
  • HSDPA demonstrator in Cellular Telephone Industry Association(CTIA) Wireless Tradeshow, “the Most Important Technology Event of the Year”, New Orleans, 2003.
  • Session chairs for the IEEE Vehicular Technology Conference (VTC)’05, Dallas, TX, and IEEE Wireless and Communications Network Conference (WCNC)’06, Las Vegas, 2006.
  • Member, Institute of Electrical and Electronics Engineers, Circuit and System Society, Communications Society, 2002-present.
  • Reviewer of IEEE Transactions on Circuits and Systems, EURASIP Journal on Embedded Systems, IEEE Vehicular Technology Conference (VTC), IEEE International Conference on Communications (ICC), IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Trans. on Wireless Communications, Reviewer of Wireless Communications and Mobile Computing Journal, John Wiley & Sons, Transactions of IEICE (Institute of Electronics, Information and Communication Engineers),
  • Reviewer of various patent applications, 2004-2006.

 

Teaching

  • TA of ELEC 241 and ELEC 422/423 and ELEC424 in Rice University, Peking University.

 

Major R&D Contributions Summary

1.        Algorithms & Architecture Research for Wireless Communication

o        Baseband + Digital Front-End (DFE) for low cost, SoC solution of Femto Home BTS, 2007. Responsibility covers solution development, PHY algorithm and SoC Spec, SoC architecture design and proto

§         Algorithms: Femto-optimized BB+DFE, multi-radio BTS, Rake/equalizer tradeoff, F-domain EQU for multi-radio (HSPA, WiMax and LTE)

§         Architecture: multi-core BB SoC  tech. eval(ARM Ardbeg,STMicro, NXP Vector Processor, and Sandbridge multi-core DSP, embedded SW/HW acceleration partition/design, multi-Gbps SRIO

o        Baseband (MIMO) and RF (Envelop Tracking DFE, Digital Pre-distortion) for LTE Macro BTS PofC, 2006: responsible for the DL BB implementation spec (channel coding, MIMO etc), Matlab modeling, complexity analysis etc.

o        Soft Sphere detection/decoding for MIMO-OFDM systems.

o        PROM-DET: Practical Near-optimal MIMO Detection/decoding, an implementation perspective.

o        VLSI Architecture for Iterative Soft-Information Lattice Space-time (LAST) Decoding, 2005.

o        CDMA Algorithmic Research for Real-time Implementation, low complexity MMSE equalizer 2003-2005.

o        MIMO-OFDM Detection/Decoding Architecture for WiMax,4G, 2004.

o        Power efficiency and PAPR of multi-tier wireless systems, 2000-2002.

 

2.        Real-time Hardware System Prototyping

o        HW/SW ((FPGA /DSP) partitioning and design, multi-Gbits/s Serial I/O for LTE BTS Proof-of-Concept, 2006.

§         Focus on the UL RX BB functions and DL DFE functions (CFR, DPD, interpolation and filtering) and inter-chip SRIO on FPGA.

o        HW/SW (FPGA/DSP) partitioning and design for LTE BTS PofC, multi-Gbits/s serial I/O, 2006.

o        MIMO Multi-Carrier CDMA (OFDM-CDMA) demonstrator based on FPGA: implemented most BB functions (detection, equalization, channel estimation, demodulation, etc).

o        Design for Field Trial System for WCDMA/HSDPA:  small form factor, with MMSE equalizer, RX diversity.

 

3.        System-on-Chip Design Methodology

    • Evaluated various Electronics Design Automation (EDA) methodologies, including SystemC, HandelC, Accelechip, HDL Designer, Eves design system
    • Derived an efficient integrated High-Level-Synthesis (HLS) design methodology for wireless systems by Catapult-C, increased the productivity significantly for VLSI based system prototyping

 

4.        Networking/Software

    • Transmission Scheduling on Shared Channel of 3G Air Interface, Rice University, fall 2000.
    • Intelligent Network solutions for mobile telecommunication network architecture, Bell Labs, 1999.
    • Multi-threaded IPX/SPX and TCP/IP network Server in Unixware 2.1, BUPT, 1997-1998.
    • Intelligent Switching Platform of Integrated Information System, M.S. thesis work, BUPT, 1997-99.

 

5.        Multimedia Communication and Signal Processing

    • Research on MPEG-4 standard, Multi-Layered Transmission of Video in ATM Environment,
    • A general analysis and processing system of image on windows, awarded as Excellent Software for Exhibition in the 1st National College Computer Competition.
    • Low-Bit Rate CELP Speech Codec for CDMA IS-96, 1997.
    • Applications of Wavelet, adaptive filter for Sonar signal processing
    • GEL-LAB Molecular Gel Image Analysis and Processing System

 

Refereed Publications

For a complete list of publications and for downloading papers in pdf format please visit the Rice CMC document database.

 

  1. P. Radosavljevic, Y. Guo, J. R. Cavallaro, Probability based Bounded Soft Sphere Detection for MIMO-OFDM Systems: system and VLSI Architecture, to be submitted to IEEE Trans. Circuits and Systems I, 2007.

 

  1. Y. Guo, J. Zhang, D. McCain, J. R. Cavallaro, Structured parallel architecture for displacement MIMO Kalman equalizer in CDMA systems, IEEE Trans. On Circuits and Systems II, Vol. 54, pp. 122-126, Feb. 2007.

 

  1. Y. Guo, D. McCain, J. R. Cavallaro, Rapid Industrial Prototyping and Scheduling of 3G/4G SoC Architectures with HLS Methodology, accepted for publication in EURASIP Journal on Embedded Systems, special issue on Signal Processing with High Complexity, Vol. 2006, article ID 14952, 2006.

 

  1. Y. Guo, J. Zhang, D. McCain, J. Cavallaro, An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture, EURASIP Journal on Applied Signal Processing 2006 (2006), Article ID 57134, 18 pages.

 

  1. Y. Guo, D. McCain, Rapid Prototyping and VLSI Exploration for 3G/4G MIMO Wireless Systems Using Integrated Catapult-C Methodology, IEEE Wireless Communications and Networking Conference (WCNC), pp. 958- 963, Las Vegas, April, 3-6th, 2006.

 

6.        Y. Guo, J. R. Cavallaro, A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems, Journal of VLSI signal processing Systems for Signal, Image and Video Technology, Vol. 44, pp. 195-217, Sept. 2006.

 

  1. Y. Guo, J. Zhang, D. McCain, J. Cavallaro, Displacement MIMO Kalman equalizer architecture for CDMA downlink in fast fading channels, submitted to IEEE Trans. on Wireless Communications, 1st revision under review, July, 2005.

 

  1. Y. Guo, Advanced MIMO-CDMA Receiver for Interference Suppression: Algorithms, System-on-Chip Architectures and Design Methodology, Ph.D. Thesis, Rice University, Houston, TX, May 2005.

 

  1. Y. Guo, J. Zhang, D. McCain, J. Cavallaro, Displacement MIMO Kalman Equalizer for CDMA Downlink in Fast Fading Channels,  IEEE Globecom 2005, pp.2281-2286, St. Louis, MO, Nov. 28th-Dec. 2nd,  2005.

 

  1. Y. Guo, D. McCain, Pipelined and Reduced QRD-M Detector in MIMO-OFDM Systems With Partial and Embedded Sorting, IEEE Globecom 2005, pp.187-192, St. Louis, MO, Nov.28th-Dec. 2nd, 2005.

 

  1. Y. Guo, D. McCain, J. Cavallaro, Low Power VLSI Architecture for Adaptive MAI Suppression in CDMA Using Multi-stage Convergence Masking Vector, IEEE Vehicular Technology Conference (VTC), pp.1761-1766, Dallas, TX,  Sep. 28th 2005.

 

  1. Y. Guo, D. McCain, J. Cavallaro, Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink, IEEE VTC, pp. 2096-2101, Dallas, TX, September 28th 2005.

 

  1. Y. Guo, D. McCain, J. Cavallaro, FFT-Accelerated Iterative MIMO Chip Equalizer Architecture For CDMA Downlink, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Vol. 3, pp.1005 - 1008, March 18-23, 2005.

 

  1. Y. Guo, Efficient VLSI Architectures for Recursive Vandermonde QR Decomposition in Broadband OFDM Pre-distortion, IEEE Wireless Communications and Networking Conference (WCNC), Vol.1, pp.589 - 595,13-17 March 2005.

 

  1. Y. Guo and D. McCain, Untimed-C based SoC Architecture Design Space Exploration for 3G and Beyond Wireless Systems, Design and Verification Conference, San Jose, CA, February 2005.

 

  1. Y. Guo, J. Zhang, D. McCain, J. Cavallaro, Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study, IEEE GlobeCom, pp. 2513 - 2519, Volume 4, No. 7, Dallas, Tx, (November 2004).

 

  1. Y. Guo, D. McCain, Compact Hardware Accelerator for Functional Verification and Rapid Prototyping of 4G Wireless Communication Systems, IEEE the 38th Asilomar Conference on Signals, Systems and Computers, Vol. 1, pp.767-771, 7-10 Nov. 2004.

 

  1. Y. Guo, D. McCain, J. Cavallaro, Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems, IEEE International Symposium on Circuits and Systems (ISCAS),  pp:IV - 77-80, Volume 4, No. 4, Vancouver, Canada, May 2004.

 

  1. Y. Guo, D. McCain, J. Zhang, J. Cavallaro, Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink, IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 2171 - 2175, Volume 2, Monterey, CA, November 2003.

 

  1. Y. Guo, D. McCain, G. Xu, J. Cavallaro, Rapid Scheduling of Efficient FPGA Architectures for Next-Generation HSDPA Wireless System Using Precision C Synthesizer, IEEE International Workshop on Rapid Systems Prototyping (RSP'03), pp. 179-185, San Diego, CA,, June 2003.

 

  1. Y. Guo, J. Cavallaro, Enhanced Power Efficiency of Mobile OFDM Radio using Pre-distortion and Post-compensation, pp.214-218, IEEE Vehicular Technology Conference (VTC), Vancouver, Canada, September 2002.

 

  1. Y. Guo, J. R. Cavallaro, Reducing Peak-to-Average Power Ratio in OFDM Systems by adaptive dynamic range companding, Proceeding of 3G Wireless and World Wireless Congress, San Francisco, CA, USA, May 2002.

 

  1. Y. Guo, J. R. Cavallaro, Post-Compensation of RF Non-Linearity in Mobile OFDM Systems by Estimation of Memory-less Polynomial,  IEEE International Symposium on Circuits and Systems (ISCAS), pp.I217-I220, Phoenix, AZ, May 2002.

 

  1. Y. Guo, J. R. Cavallaro, A Novel Adaptive Pre-Distorter Using LS Estimation of SSPA Non-Linearity in Mobile OFDM Systems, IEEE International Symposium on Circuits and Systems (ISCAS), pp. III453-456, Phoenix, AZ, USA, May 2002.

 

  1. Y. Guo, H. Zhou, X. Wang, J. Cavallaro, VLSI Implementation of Mallat's Fast Discrete Wavelet, IEEE Globecom pp.320-324, San. Antonio, TX, November 2001.

 

  1. Y. Guo, B. Wen, Q. Li, et.al., Real time extraction of targets' parameter of sonar by wavelet on TMS320 DSP, IEEE  International Conference on Communication Technologies (ICCT), pp.S36.04.1-S36.04.5, Beijing, China, 1998.

 

Technical Reports

  1. Y. Guo, “Hardware feasibility study and fixed-point implementation of Sigs2D lattice decoder”, NRC tech report, 2005.
  2. Y. Guo, T. Bhatt, M. Heikkila, D. McCain, Superfast parallel space-time linear MMSE equalizer for communications, submitted NRC invention report NC17815, 2005.
  3. Y. Guo, G. Xu, K. Anand, D. Mccain, “Real-time FPGA implementation of time-domain equalizer using generalized Schur Algorithm for outdoor OFDM systems”, Nokia Research Center, technical report, Sept. 2001.
  4. B. Jones, M. Gadhiok, Y. Guo, S. Rajagopal, “Rapid prototyping for digital signal processing algorithms”, Rice University RENE project technical report, 2001.
  5. Y. Guo, J. Cavallaro, B. Aazhang, A. Sabhaval, “Wideband RF modeling & baseband design for W-CDMA systems”, Rice University, RENE Technical report & PhD qualifying report, 2000.

 

Funding Support

  • Supported by NSF funds: “Seamless Multi-tier Wireless Networks for Multimedia Applications,” NSF ANI-9979465, $700,000, 1999-2003, (J. R. Cavallaro (Co-PI) with B. Aazhang (PI), R.G. Baraniuk (Co-PI), E.W.Knightly (Co-PI), and D.S. Wallach (Co-PI)).
  • Supported by “Leadership University: New Applications of DSPs in Networking and Integrated Wireless Sensors,” Texas Instruments, Inc., J. R. Cavallaro (Co-PI), $1,000,000, 1999-2001, (with C. S. Burrus (PI), B.Aazhang (Co-PI), E. W. Knightly (Co-PI), and R. G. Baraniuk (Co-PI)).

 

Public Presentations & Media Report

·         “Rapid Scheduling of VLSI Architectures for Wireless Systems Using Catapult-C”, IEEE Design Automation Conference Expert Panelist, 2004.

·         3G Mobile  article on World’s first HSDPA demonstrator in CTIA 2003.

·         http://press.nokia.com/PR/200303/895755_5.html

·         http://www.unstrung.com/document.asp?doc_id=29784

·         http://www.umts-forum.org/servlet/dycon/ztumts/umts/Live/en/umts/News_3GArchive_2003_JanMar_Article170303a

 

Technical Skills

Implementation Platforms:

  • Xilinx/Altera FPGAs (physical layer of the Multi-carrier CDMA, OFDM, HSDPA demonstrators)
  • Texas Instrument's  DSP, Code Composer (Used for the digital sonar design and portable information system)
  • Aptix and Nallatech FPGA DSP platform, WildCard FPGA PCMCIA card, HP/Agilent’s logic analyzer.
  • Windows, UNIX/UnixWare, Network (TCP/IP & SPX/IPX), Concurrent Client/Server Applications.

 

Design Tools:

  • Mentor Graphics design flow (Catapult-C, HDL Designer, ModelSim, Leonardo, Precision RTL synthesis tools).
  • Cadence SPW, HDS, Synopsis and Synplicity synthesis tools.
  • Modeling/simulation with matlab/simulink, systemView, mixed signal modeling (high speed AD/DA, up/down conversion), familiar with Intersil PRISM II WLAN chip-set.
  • Language: ANSI C, Visual Studio (C++, VB etc), VHDL/Verilog, mixed C/ASM for DSP, and MSC51 monolithic Systems, Protel CAD tools, VLSI design CAD tools (magic, irsim, crystal, spice etc).
  • Experience with Delphi, Java, perl.

 

Personality:

  • Highly Self-motivated, independent work experiences
  • Teamwork and communication skills in multi-culture international company

 

Personal:  Citizen of P. R. China, H1-B working Visa, green card application portable.

 

References (Available upon request)

  • Dr. Joseph R. Cavallaro, Professor of Electrical and Computer Engineering and Computer Science.
  • Dr. Behnaam Aazhang, J. S. Abercrombie Professor of Electrical and Computer Engineering, Department Head.
  • Dr. Richard A. Tapia, Noah G. Harding Professor of Computational and Applied Mathematics, Associate Director of Graduate Studies.

 

 


 

Description of Major R&D Contributions

 

Details available from http://www.ece.rice.edu/~ybguo/research.html

1. Algorithms & Architecture Research for Wireless Communication

o        

o       LTE BTS PofC algorithm and standard development

 

o       Digital Front-end and pre-distortion for Envelop Tracking RF in LTE-BTS PofC

 

o       Bounded Soft Sphere Decoding in MIMO-OFDM systems

 

o       Practical Near-optimal MIMO Detection/decoding (PROM-DET), an implementation perspective.

MIMO detection/decoding is a major bottleneck in realizing the break-through multi-antenna technology for high data-rate future wireless systems. The optimal Maximum-Likelihood (ML) detection is NP-hard for practical implementation because of its prohibitively high complexity. However, the current sub-optimal solutions such as VBLAST, MMSE/ZF linear detectors are far from achieving the promised MIMO channel capacity. In this project, I acted as the project manager to explore near-optimal MIMO detection technologies which will enable real-time implementation and approach the channel capacity. This involves a comprehensive survey and architecture feasibility study on the cutting-edge advances in both algorithms research and real-time architectures. I focused on sphere decoding, lattice decoder, semi-definite-programming algorithms and explored the parallel architectures for these promising algorithms. This research is targeted to benefit the future WiMax, WLAN and mesh network concepts using multi-antenna technologies.

 

o       Architecture for Iterative Soft-Information Generic Sphere Detection/decoding (Sigs2D)

I acted as the principle investigator to explore the architecture of some iterative Lattice Space-time Coding/decoding (LAST) receivers which favor the real-time implementation. My focus was on the hardware implementation issues. In this research, I proposed a structured MMSE Interference Cancellation iterative receiver architecture with reduced complexity. I also proposed efficient VLSI architectures for a generic LAST receiver using Tanner Graph representation and non-Binary Belief-Propagation algorithm. The commonality between this receiver and LDPC channel coding is explored to reduce the overall receiver system complexity.

 

o       CDMA Algorithmic Research for real-time implementation

I have worked extensively for the algorithm design of various receiver algorithms for WCDMA, HSDPA, CDMA2000, 1xEV-DV/DO standards. These include various low complexity equalizers for single and multiple antenna systems, as well as interference cancellation for CDMA related technologies. I proposed a super-fast parallel LMMSE equalizer for the space-time communication systems. The work solved the notorious numerical stability problem in the fixed-point matrix-inverse based channel equalizers. It has the lowest implementation complexity in the literature to our knowledge. The parallel architecture achieves the best performance/complexity tradeoff. My working domain covers from the algorithm design, fixed-point analysis, RTL design and VLSI hardware validation, to the final system integration in real-time prototyping platforms.

 

This is part of my PhD dissertation carried in Rice University. Interference is the major limiting factor to the MIMO systems. Advanced signal processing algorithms are required to achieve favorable performance. However, this leads to tremendous challenges in real-time implementation because of the increased system complexity. In this work, I proposed various low-complexity, parallel algorithms which are more suitable for VLSI/DSP real-time implementation. Some key contributions include FFT-based linear MMSE equalizers, displacement Kalman filter, Conjugate-Gradient equalizer, and low-power parallel interference cancellation etc. This work leads to four filed US patents. I also explored the related efficient VLSI architectures of these advanced receiver algorithms.

 

o       MIMO-OFDM Detection/Decoding Architecture for WiMax, 4G

As a part of the 4G concept program, I proposed a reduced QRD-M algorithm with partial and embedded sorting for the detection of MIMO-OFDM systems. The proposed algorithm achieves significant complexity reduction in both the metric computation and the trellis search. The algorithm was implemented in an FPGA platform. A detailed feasibility and complexity analysis of the 4G concept system was carried out to support a real-time prototyping of the 4G system. I was also involved in the development of low-complexity LDPC codes with application to UWB, 802.11n and 802.16e.

 

o       Power efficiency enhancement of multi-tier wireless systems

Power efficiency is essential for the portable devices. Non-linearity and high peak-to-average power ratio (PAPR) limit the power efficiency of systems with multiple signal levels. In this work, I proposed advanced wireless communication algorithms to enhance power efficiency of wireless communication systems by methods of Peak-to-average-power ratio (PAPR) reduction, power control and non-linearity compensation; Designed adaptive pre-distortion and post-compensation with super-fast Vandermonde solvers and Levinson-type algorithms; I also proposed efficient implementation architectures for the Levinson-type Vandermonde QR-decomposition for non-linearity equalization. The objective was to support the Rice Everywhere NEtwork (RENE) project, a multi-tier network system. However, it could find application for any civil and military portable devices.

 

2.      Real-time Hardware System Prototyping

 

 

    • MIMO Multi-Carrier CDMA (OFDM-CDMA)

The purpose of this project is to support the 3.5G standardization with 3GPP2 CDMA-Air Interface. I was in charge of the FPGA design for end-to-end base band and the system-level integration. My responsibility in FPGA design includes all the modules in the OFDM frequency domain from MMSE channel estimation, equalizer, soft-information, to filter compensation, etc. I was also in charge of the MIMO evolution of the real-time system. Key features include high data rate up to 11.4Mbps, high-order modulation up to 16-QAM, and link adaptation. An over-the-air demonstration was shown successfully in the NRC Day in Dallas, TX.

 

I was in charge of the design of a super-fast space-time chip-level equalizer, which is an essential enabler for the field trial in multi-path channels. My responsibility covered from fixed-point design and architecture specification, to the actual FPGA design and validation. The field system was built on a customized Nallatech real-time system with multiple FPGA on a stack with compact form factor. The field-trial platform is fully programmable and can be easily used for any other radio demonstrators.

 

HSDPA (High Speed Downlink Packet Access) marks a similar boost for WCDMA that EDGE does for GSM. It provides a two-fold increase in air interface capacity and a five-fold increase in data speeds in the downlink direction. As a member of the core team, I designed and demonstrated the first release of this kind of HSDPA real-time prototype system in the world. My role was designing FPGA base band core algorithms (e.g., chip equalizer, clock-tracking, configurable turbo-interleaver for turbo codes, automatic frequency control etc), porting the baseband design to a Nallatach BenNUEY multiple FPGA platform, and system integration with both RF front-end and DSP MAC layer. System was demonstrated successfully in the Cellular Telephone Industry Association (CTIA) Wireless Tradeshow in 2003, the most important wireless technical event in the Americas. After the tradeshow, the system was set up in an intelligent truck and demonstrated globally in seven countries. Video and news release is available here. The demonstration video clip highlights the main features of HSDPA by showing the following: 1). a DVD-quality streaming video application running over a complete HSDPA radio system. In this demonstration, the layer 1 supports of data-rate of up to 10Mbps; 2). the link adaptation feature by showing how the signal constellation changes from 16-QAM (Quadrature Amplitude Modulation) to QPSK (Quadrature Phase Shift Keying) by introducing interference in the wireless link.

More news release could be found at:

3G Mobile  article:

http://press.nokia.com/PR/200303/895755_5.html

http://www.unstrung.com/document.asp?doc_id=29784

http://www.umts-forum.org/servlet/dycon/ztumts/umts/Live/en/umts/News_3GArchive_2003_JanMar_Article170303a

 

In this work, I studied the FPGA architecture of a complex time-domain equalizer for outdoor OFDM WLAN systems using Generalized Schur Algorithm. As the most complicated block in the 54Mbps 802.11a OFDM system, the equalizer was implemented and tested successfully in Xilinx Virtex-E 2000 FPGAs at the speed of 34 ms for 24 taps complex channel.

 

RENE (Rice Everywhere Network) is a multi-tier wireless network concept cross W-CDMA and WLAN. In this project, I was in charge of the real-time implementation issues for a re-configurable platform with DSP, FPGA, ASIC and high-speed digital transceiver and software RF solutions (DDS/DDC). I also completed an end-to-end system modeling with analog RF transceiver in the chain. The Wideband RF modeling and baseband Design for W-CDMA system evaluated a Digital Direct Synthesizer (DDS) and Digital Down Converter (DDC) transceiver using SystemView/matlab (my PhD Qualifying Project).

 

I proposed some reduced complexity DWT architecture and implemented an ASIC chip in the VLSI design course project. The chip was fabricated through MOSIS.

 

JPEG codec standard and iButton touch memory technology. Under editing…

 

Using spectrum-analysis to detect passive sonar noise and active-sonar Doppler Frequency Shift in digital Sonar systems, implemented digital beam forming in circular array Sonar systems on TI’s DSP platform. This was my undergraduate thesis work carried out during 10/1995-06/1996 in the Signal Processing Lab, Institute of Acoustics, Chinese Academy of Science, Beijing, China.

 

3.      System-on-Chip Design Methodology

    • In this work, I evaluated many EDA tools Accelechip, Eve Xilinx, etc.….
    • Derived an efficient Catapult-C based rapid prototyping methodology for FPGA implementation. The rapid architecture scheduling prototyping methodology improves the efficiency dramatically, saving the time-to-market for a typical wireless system development by more than 70%.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.      Networking/Software

         These were mainly accomplished while I worked for Bell Labs and in BUPT.

Accomplished several projects in the Department of Intelligent Network, Asian Pacific Communication Software Center. Focused on TCAP layer of SS7 communication protocols in SCPs and provided IN solutions for mobile networks such as GSM MSC, IS54 etc.

    • Multi-threaded IPX/SPX and TCP/IP network Server in Unixware 2.1, Voice Mailbox and Automatic Speech Server in a Paging System, Based on AG-E1 Speech Card of Dialogic Inc., Software Architect and major programmer. 1997.10-1998.4.
    • Intelligent Switching Platform of Integrated Information System, software system architect and team-leader of a 10-member team, main software designer, Multimedia Communication Center of BUPT. 1998.1-1998.8.

 

5.      Multimedia Communication and Signal Processing

    • A general analysis and processing system of image on windows.1996.9-1997.8. Awarded as Excellent Software for Displaying and Exhibition in the 1st National College Computer Competition.
    • Low-Bit Rate CELP Speech Codec in CDMA IS-96, 1997.
    • Motion-Vector Estimation in Image Sequence Processing System and Multi-Layered Transmission of Video in ATM Environment, other problems on Image Sequence Processing System, 1997.
    • A general Analysis and Processing System of Gray Image on Windows. Awarded by the 1st National College Computer Competition Committee as Excellent Software for Exhibition.
    • GEL-LAB Molecular Gel Image Analysis and Processing System on windows, Software Designer and Programmer, Summer Employment in Metronics Corporation, 1996.6—1996.10.

 

Fig. 1. 3G Mobile media report on the HSDPA demonstrator by my team.

Fig. 2. The design team of the HSDPA demonstrator in CTIA 2003, New Orleans.

 

Fig. 3. With John Zhang in the HSDPA demonstrator booth, CTIA, 2003.

 

Fig. 4. The setup of the HSDPA demonstrator in CTIA.

 

Fig. 5. An overview of the HSPDA demonstrator: base-station on the left, mobile station on the right.

 

Fig. 6. Setup of HSDPA demonstrator in the intelligent truck for tradeshows around the world.