|
|
Research
Interest
- Wireless multimedia communication networks,
sensor networks, CDMA, HSPA, OFDM, LTE, Femto home BTS
- Equalization, detection and coding for multiple
antenna/sensor systems, MIMO, space-time codes
- Parallel algorithms and high-speed VLSI DSP
architecture
- Real-time embedded systems design and
prototyping, System-on-Chip
Major R&D Contributions Summary
1.
Algorithms
& Architecture Research for Wireless Communication
o
Baseband + Digital Front-End (DFE) for low cost, SoC
solution of Femto Home BTS, 2007. Responsibility covers solution
development, PHY algorithm and SoC Spec, SoC architecture design and
proto
§
Algorithms: Femto-optimized BB+DFE, multi-radio BTS,
Rake/equalizer tradeoff, F-domain EQU for multi-radio (HSPA, WiMax and
LTE)
§
Architecture: multi-core BB SoC tech. eval(ARM Ardbeg,STMicro, NXP
Vector Processor, and Sandbridge multi-core DSP, embedded SW/HW
acceleration partition/design, multi-Gbps SRIO
o
Baseband (MIMO) and RF (Envelop Tracking DFE, Digital
Pre-distortion) for LTE Macro BTS PofC, 2006: responsible for the DL BB
implementation spec (channel coding, MIMO etc), Matlab modeling,
complexity analysis etc.
o
Soft Sphere detection/decoding for MIMO-OFDM systems.
o
PROM-DET: Practical
Near-optimal MIMO Detection/decoding, an implementation perspective.
o
VLSI Architecture for Iterative Soft-Information
Lattice Space-time (LAST) Decoding, 2005.
o
CDMA Algorithmic Research
for Real-time Implementation, low complexity MMSE equalizer 2003-2005.
o
MIMO-OFDM Detection/Decoding
Architecture for WiMax,4G, 2004.
o
Power efficiency and
PAPR of multi-tier wireless systems, 2000-2002.
2.
Real-time Hardware System Prototyping
o
HW/SW ((FPGA /DSP)
partitioning and design, multi-Gbits/s Serial I/O for LTE BTS
Proof-of-Concept, 2006.
§
Focus on the UL RX BB
functions and DL DFE functions (CFR, DPD, interpolation and filtering)
and inter-chip SRIO on FPGA.
o
HW/SW (FPGA/DSP)
partitioning and design for LTE BTS PofC, multi-Gbits/s serial I/O, 2006.
o
MIMO Multi-Carrier CDMA
(OFDM-CDMA) demonstrator based on FPGA: implemented most BB functions
(detection, equalization, channel estimation, demodulation, etc).
o
Design
for Field Trial System for WCDMA/HSDPA: small form factor, with MMSE equalizer,
RX diversity.
3.
System-on-Chip Design Methodology
- Evaluated various
Electronics Design Automation (EDA) methodologies, including
SystemC, HandelC, Accelechip, HDL Designer, Eves design system
- Derived an efficient
integrated High-Level-Synthesis (HLS) design methodology for
wireless systems by Catapult-C, increased the productivity
significantly for VLSI based system prototyping
4.
Networking/Software
- Transmission
Scheduling on Shared Channel of 3G Air Interface, Rice University,
fall 2000.
- Intelligent Network
solutions for mobile telecommunication network architecture, Bell Labs,
1999.
- Multi-threaded
IPX/SPX and TCP/IP network Server in Unixware 2.1, BUPT, 1997-1998.
- Intelligent Switching
Platform of Integrated Information System, M.S. thesis work, BUPT,
1997-99.
5.
Multimedia Communication and Signal
Processing
- Research on MPEG-4 standard,
Multi-Layered Transmission of Video in ATM Environment,
- A general analysis and
processing system of image on windows, awarded as Excellent
Software for Exhibition in the 1st National
College
Computer Competition.
- Low-Bit Rate CELP Speech
Codec for CDMA IS-96,
1997.
- Applications of Wavelet, adaptive filter
for Sonar signal processing
- GEL-LAB Molecular Gel Image Analysis and
Processing System
|
|
