MOSIS Project Report

REQUEST	 	REPORT
FAB ID	 	N5CRCD1
PROJECT NAME  	joaped
DESIGNER NAME 	Aparna Ambani    PHONE : (713) 741 6216      aparna@rice.edu
		Gary Herd	         (713) 527 4020      garyherd@rice.edu
		Josh Roper		 (713) 630 8960      jmr@rice.edu
ORGANIZATION	Rice University
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SHIPPING		Chips arrived in good condition	Ã
			Chips damaged during shipping	0
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PACKAGING	
Overall Quality : 	GOOD	Ã	PROBLEMS	     NO
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PERFORMANCE	
			# parts received : 4		# parts functional : 4
Possible reasons for failures	 NA
Mask Defect		Wafer Defect		Packaging		Design  
Speed compared to simulation	17MHz (According to design calculations)
Perfromance compared to other fabrications  : seemed to be better than other in the run.
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COMMENTS	No Problems found
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WWW URL		http://www.owlnet.rice.edu/~aparna/vlsi.html 

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 Function Description 


Project : Implementation of 8-bit ALU 

Our design project is to build an 8-bit ALU. The ALU will perform addition and 
subtraction. The chip we design will also include a shift function, separate 
from the adder. Input will enter during two clock cycles for addition and 
subtraction. There will be eight single bit inputs which will go to input 
register one during the first clock cycle. 

During the second clock cycle the inputs will go to input register two.
If the operation is a shift operation, the input will go from input register
one to the shift and output register during the second clock cycle. If this is
the case, then input register two will not receive any data during the second 
clock cycle. 

Also, we are supporting all memory operations in this design. For all 
operations, addition, subtraction, shift left (by 1, 2 or 3 bits) and shift 
right (by 1, 2 or 3 bits) can get their one operand from the memory. Results 
are stored in the memory which can be used in next operation as an operand 
which will allow the sequence of operations.

The control receives four bit input during the first clock cycle. It will 
interpret the input to be addition, subtraction, or one of the shift operations.
The control will then send a signal to the input registers so that on the 
second clock cycle it will either receive a second input or move the first 
input to the Barrel Shifter The control will also tell the adder whether it 
is an add or subtract operation, or if it will be idle for a shift operation. 
It will also tell the shift register if it is idle or the type of shift.
During addition and subtraction, the inputs will move to the adder, where 
the operation will occur using modified carry look-ahead(CLA) logic. 
The CLA has been modified to reduce the fan-in and fan-out which will result 
in increase of speed. The adder will send the solution to the shift and output 
register, where it will then wait to be output to the user.