ADDER-SUBRACTOR UNIT

ADDER-SUBTRACTOR UNIT : This unit implements the addition and subtraction functions as required by out ALU circuit.

After comparing different algorithms like Ripple Carry , Carry completion, Carry save , Carry-look ahead and Conditional sum adder, we have selected CARRY-LOOKAHEAD considering the complexity, number of gates required and the total delay time.

The basic algorithm for the Carry-lookahead can be described as under.

As the name suggests, carries entering all the bit additions are generated simultaneously by additional logic circuitry. This results in a constant addition time independent of the length of the adder.

Let A and B be the n bit numbers., Ci-1 be the carry input the ith bit position Let Si and Ci be the sum and carry outputs of the ith stage. Si and Ci can be given as under. Besides that we define two auxiliary functions as follows :

Si = Ai EXOR Bi EXOR Ci

Ci+1 = AiBi + BiCi + CiAi

Gi = AiBi

Pi = Ai OR with Bi

The carry generate function Gi reflects the condition that a carry is originated at the ith stage. The function Pi called carry propogate, is true when the ith stage will pass the incoming carry Ci-1 to the next higher stage. Implementation is shown as Carry Generate/Propogate Unit(fig.) and Summation Unit(fig.) Substituting Pi and Gi, we can obtain values for Si and Ci. Also it is the fact that all Pi and Gi for all n-1 bits can be generated simultaneously from the external inputs A and B. Now for genrating carry we can apply recursive formula and can obtain the carry equations in terms of Pi's and Gi's and initial carry., and so all Si bits can be generated in parallel. All the carry equations can be realized with a combinational logic unit, known as Carry Lookahead Unit(fig.)

Now, combining three different units like Carry Generate/Propogate Unit, Summation Unit and Carry Lookahead Unit, we can implement a carry lookahead adder for 8 bits binary numbers as shown in fig.

We incorporate subtraction by using carry input Ci-1 and also using multiplexer at the B input with control signal as mode bit.

We are also planning to implement addition and subtraction of signed numbers.