ABCPU2
Instruction Set
Briefly, we chose the accumlator style architecture in order to simplify
our instruction set. With only a four-bit CPU, and a four-bit opcode in our
implementation, adding any more registers would be superfluous and
difficult to design and build.
Instruction Set
Our instruction set is as follows:
| Instruction | Opcode | Operands | Function |
| ZERO | 0000 | n/a | clears accumulator to 0 |
| n/a | 0001 | n/a | n/a |
| CIRC | 0010 | n/a | circulates acc. |
| NOT | 0011 | n/a | inverts acc |
| ANDI | 0100 | immediate | acc = acc & immediate |
| ORI | 0101 | immediate | acc = acc | immediate |
| ADDI | 0110 | immediate | acc = acc + immediate |
| LDI | 0111 | immediate | acc <- immediate |
| BEZ | 1000 | address | PC <- address if acc = 0 |
| BGZ | 1001 | address | PC <- address if acc > 0 |
| LD | 1010 | address | memory(address) -> acc |
| ST | 1011 | address | acc -> memory(address) |
| AND | 1100 | address | acc = acc & memory(address) |
| OR | 1101 | address | acc = acc | memory(address) |
| ADD | 1110 | address | acc = acc + memory(address) |
| SUB | 1111 | address | acc = acc - memory(address) |
General Comments on Instruction Set
With our four-bit machine, we chose four-bit opcodes with either zero, four,
or eight-bit operands. The opcodes are chosen such that ALU operations are
distinguished from other operations by having the high bit of the opcode set,
and within the two major divisions, other opcodes are "grouped" and have
close (in the hamming sense) bit representations. In the final version of
the instruction set, immediates are four bits and addresses are eight bits.
That means that accumulator-memory ALU operations have 12-bit instructions
(opcode plus address), as do load and store from and to memory as well as
branches; register-immediate ALU operations and load-immediate operations have
8-bit instructions (opcode plus data), and instructions with no operands are
four bits. For the most part, the machine spends two cycles per four bits of
data read (including opcode), which means that a no-operand instruction takes
two cycle (three in practice, since we have to execute the instruction without
doing useful data-bus transfers); operations with immediate data take four
cycles; and operations with data from memory addresses take six cycles (seven
for ALU operations from memory).
Last modified 19 December 1996.