We tested several sample "code fragments" for our CPU, and the programs we used for our final simulations are included below. We also have the irsim output of code fragment #8, which simulates a load-immediate, and addition, and a store.
| ABCPU2 - The Final Simulation | | Scot Salmon, Todd Stadler, Jason Nearing | stepsize 1000ns clock Vdd 1 clock GND 0 clock Vdd-PAD 1 clock GND-PAD 0 clock clka 0 1 0 0 clock clkb 0 0 0 1 vector DATA D3 D2 D1 D0 vector DATAOUT D3-out D2-out D1-out D0-out vector STATE StBit0-PAD StBit1-PAD StBit2-PAD vector ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 | Watch data-out by watching DATAOUT vector and acc2bus signal ana reset DATA DATAOUT acc2bus-int STATE ADDRESS clka clkb error | Note that length of reset vector may cause programs to run more than once V reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | Basic functionality |V DATA 0000 0000 0000 0000 | SIMULATION VECTORS | | Recommended runs: sim-add-and (#4), sim-branch (#7), sim-store (#8) | Note that the length of the restart vector may cause your program to run | more than once. It is advisable to put some extra 0000's at the end of | your program to clear the accumulator. | 1. Loading immediate, Inversion and Zeroing (sim-invert.ps) |V DATA 0000 0000 0111 0111 0101 0101 0011 0011 0011 0011 0011 0011 0000 0000 0000 0000 | 2. Loading immediate, Circulation (sim-circ.ps) |V DATA 0000 0000 0111 0111 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0010 | 3. Loading immediate, OR-ing immediate (sim-ori.ps) |V DATA 0000 0000 0111 0111 0001 0001 0101 0101 0110 0110 0000 0000 0000 0000 | 4. Loading immediate, ADD-ing immediate, AND-ing immediate (sim-add-and.ps) |V DATA 0000 0000 0111 0111 0001 0001 0110 0110 0001 0001 0100 0100 1101 1101 0000 0000 0000 0000 | 5. Loading immediate, ADD-ing from memory (sim-add-mem.ps) |V DATA 0000 0000 0111 0111 0001 0001 1110 1110 1111 1111 1010 1010 0101 0101 0000 0000 0000 0000 | 6. Loading immediate, SUB-ing from memory (sim-sub-mem.ps) |V DATA 0000 0000 0111 0111 0010 0010 1111 1111 1010 1010 0101 0101 0111 0111 0000 0000 0000 0000 | 7. Load immediate, Branch, Load immediate (sim-branch.ps) |V DATA 0000 0000 0111 0111 0000 0000 1000 1000 0010 0010 1010 1010 0111 0111 0001 0001 0001 0001 0000 0000 0000 0000 | 8. Load immediate, ADD-ing immediate, storing result (sim-store.ps) V DATA 0000 0000 0111 0111 0001 0001 0110 0110 0001 0001 1011 1011 0010 0010 1010 1010 0000 0000 0000 0000 R