System Timing

It's all about timing. Whether you're pushing dope or pushing bits, it's all about timing. You see, I bought some time with that half a million. Bought 24 years, but it could only last so long. So I'm leaving you, baby, I'm going to Milpitas to work in the exciting field of ASIC design.

A total view of system timing requires us to examine the entire circuit in a modular fashion. The following image shows the floorplan of the circuit divided into the smallest semantically meaningful modules:

This circuit uses non-overlapping two-phase clocking; we refer to the two clocks as clock A and clock B in the following analysis. Karplus timings listed in boldface represent constraints that must be provided in order for correct (or quality) operation, whereas others represent guarantees that the system provides if the former constraints are met. Italicized outputs represent actual outputs at the pins, rather than purely internal signals.

Input Output

CLKA QA N/A

CLKB QB N/A

Data Inputs

IN7-0 VA N/A

STROBE_A QB N/A

STROBE_B QB N/A

Input Latch A VB VBSA

Input Latch B VB VBSA

XORS for /B VBSA VBSA

PLA

RESTART VA N/A

OP3-0 VBSA N/A

STROBE_OP VA N/A

SB0-4 VBSA VBSA

ST0BAR VBSA VBSA

ST1BAR VBSA VBSA

ST3BAR VBSA VBSA

ST4BAR VBSA VBSA

ASEL N/A VBSA

CLR N/A VBSA

STORE N/A VBSA

C7-C0 N/A VBSA

OUT1 N/A VBSA

OUT0 N/A VBSA

OE N/A VBSA

Boolean Unit

OR VBSA VBSA

AND VBSA VBSA

NOT VBSA VBSA

XOR VBSA VBSA

Boolean Unit VBSA VBSA

Shifter

Input glue logic (muxes) VBSA VBSA

Barrel shifter core VBSA VBSA

Adder/Multiplier

Shift & And VBSA VBSA

MUX0 VBSA VBSA

Adder VBSA VBSA

OUTSTORE VBSA (from PLA)
QA (from CLKA) QA

C7-0 strobes VBSA (from PLA)
QA (from CLKA) QA

Output registers VBSA(data)
QA(strobe) VASB

Accumulator VASB(data)
VBSA(strobe) VBSA

Output

MUX1 VASB(add/mult)
VBSA(barrel) VAVB

MUX2 VAVB VAVB

COUT N/A VAVB

Output mux VAVB(MUX2)
VBSA(boolean) VAVB

OUT_EXT7-0 N/A VAVB

(Note: STROBE_A and STROBE_B do not need to be QB for the circuit to function; this assumption was made for easier analysis. OP3-0 only need to be VA for the FSM, but these opcodes are used directly as inputs to the shifters and various muxes, for which they must be VBSA. These opcode bits should not change before OE is asserted.)

	Input	Output
CLKA	QA	N/A
CLKB	QB	N/A
Data Inputs
IN7-0	VA	N/A
STROBE_A	QB	N/A
STROBE_B	QB	N/A
Input Latch A	VB	VBSA
Input Latch B	VB	VBSA
XORS for /B	VBSA	VBSA
PLA
RESTART	VA	N/A
OP3-0	VBSA	N/A
STROBE_OP	VA	N/A
SB0-4	VBSA	VBSA
ST0BAR	VBSA	VBSA
ST1BAR	VBSA	VBSA
ST3BAR	VBSA	VBSA
ST4BAR	VBSA	VBSA
ASEL	N/A	VBSA
CLR	N/A	VBSA
STORE	N/A	VBSA
C7-C0	N/A	VBSA
OUT1	N/A	VBSA
OUT0	N/A	VBSA
OE	N/A	VBSA
Boolean Unit
OR	VBSA	VBSA
AND	VBSA	VBSA
NOT	VBSA	VBSA
XOR	VBSA	VBSA
Boolean Unit	VBSA	VBSA
Shifter
Input glue logic (muxes)	VBSA	VBSA
Barrel shifter core	VBSA	VBSA
Adder/Multiplier
Shift & And	VBSA	VBSA
MUX0	VBSA	VBSA
Adder	VBSA	VBSA
OUTSTORE	VBSA (from PLA) QA (from CLKA)	QA
C7-0 strobes	VBSA (from PLA) QA (from CLKA)	QA
Output registers	VBSA(data) QA(strobe)	VASB
Accumulator	VASB(data) VBSA(strobe)	VBSA
Output
MUX1	VASB(add/mult) VBSA(barrel)	VAVB
MUX2	VAVB	VAVB
COUT	N/A	VAVB
Output mux	VAVB(MUX2) VBSA(boolean)	VAVB
OUT_EXT7-0	N/A	VAVB