Summary
Jagged Edge (aka Supafly) implements an 8-bit ALU with boolean, addition, subtraction,
multiplication, shift, and rotate features. Although many of the subcells were simple,
the overall cell turned out to be very complicated as a result of complex routing. This
chip is expected to perform at 25 MHz and has been tested to a high degree of confidence.
References
Karplus work -- for timing.
Weste & Estragian -- for carry-lookahead adder
Division of Work by Group Members
Although we had planned on a simple division early on (and implemented the
basic subcells in this fashion), the final routing segment killed any idea of independent
work. The division roughly followed this chart:
| Basic gates | Boolean | Shifter | Adder | Multiply | PLA | Routing |
|---|
| Tim | X | | | X | | | X |
|---|
| Murthy | X | X | | | X | X |
|---|
| Vijay | | | X | | | X | X |
|---|
Comments and Suggestions on CAD tools
No major concerns.