display automatic

clock ph1  1 0 0 0
clock ph2  0 0 1 0

|| input vector a
vector a a7 a6 a5 a4 a3 a2 a1 a0

|| input vector b
vector b b7 b6 b5 b4 b3 b2 b1 b0

|| the "a" vector that the 8-bit adder sees
vector ao ao7 ao6 ao5 ao4 ao3 ao2 ao1 ao0

|| the "b" vector that the 8-bit adder sees
vector bo bo7 bo6 bo5 bo4 bo3 bo2 bo1 bo0

|| the sum vector before the latches and transmission gates
vector s s7 s6 s5 s4 s3 s2 s1 s0

|| the output vector after the transmission gates
vector o o7 o6 o5 o4 o3 o2 o1 o0


analyzer ph1 ph2 OP0 OP4 MRESET ADDOUT a ao b bo o CO OVERFLOW


|| test transmission gates
|| output should be garbage

l ADDOUT
x MRESET
h OP4
l OP0

V a 01010101
V b 10101010

R
V

|| enable the transmission gates and test addition

h ADDOUT

|| verify the correct hooking-up of data lines
V a 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000
set b 00000000

R
V

set a 00000000
V b 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000

R
V

|| simple tests
V a      00000000 01101100 01010101 00111110 11111000 11001100
V b      00110011 00000000 10101010 00000011 10001000 00011111

||    o= 00110011 01101100 11111111 01000001 10000000 11101011
|| cout= 0        0        0        0        1        0
||   of= 0        0        0        0        0        0

R
V

|| overflow tests
V a      01010101 01111110 10000000 10000000 01111111
V b      01010101 00001000 11111111 10000000 00000001

||    o= 10101010 10000110 01111111 00000000 10000000
|| cout= 0        0        1        1        0
||   of= 1        1        1        1        1

R
V

|| test subtraction

h OP0

|| simple tests
V a      00000000 01101100 01010101 11111111 10000000 01111111 00000001
V b      00110011 00000000 01010101 10000000 11111111 00000001 01111111

||    o= 11001101 01101100 00000000 01111111 10000001 01111110 10000010
|| cout= 0        1        1        1        0        1        0
||   of= 0        0        0        0        0        0        0

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V

|| overflow tests

V a      10000000 01111111 01010101 11101100
V b      00000001 11111111 10101010 01110000

||    o= 01111111 10000000 10101011 01111100
|| cout= 1        0        0        1
||   of= 1        1        1        1

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|| test multiplication
|| emulate the self-shifting b-register and pretend there's a self-shifting
|| output register

l OP4
l OP0

h MRESET
set a 11111111
set b 11111111

c

l MRESET
V b 01111111 00111111 00011111 00001111 00000111 00000011 00000001 00000000

|| o= 1111111000000001

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|| more
h MRESET
set a 10001001
set b 00101010 

c

l MRESET
V b 00010101 00001010 00000101 00000010 00000001 00000000 00000000 00000000

|| o= 0001011001111010

R
V