Crystal, v.2 : build addmult_1_out.sim [0:00.1u 0:00.1s 24k] : : clear [0:00.0u 0:00.0s 33k] : inputs ph2 -ph2 sumin [0:00.0u 0:00.0s 33k] : outputs ssum [0:00.0u 0:00.0s 33k] : check Marking transistor flow... Setting Vdd to 1... Setting GND to 0... No flow through FET: g=ADDOUT, s=sumin, d=sumout, loc=64,180 Maybe you haven't marked all the inputs and outputs? Node isn't driven: ADDOUT (see gate at 64,180) Maybe you haven't marked all the inputs and outputs? Node doesn't drive anything: sumout (see drain at 58,190) Maybe you haven't marked all the inputs and outputs? Node isn't driven: sumout (see drain at 58,190) No flow through FET: g=-ADDOUT, s=sumin, d=sumout, loc=58,190 Node isn't driven: -ADDOUT (see gate at 58,190) [0:00.0u 0:00.0s 33k] : set 1 ph2 [0:00.0u 0:00.0s 33k] : set 0 -ph2 [0:00.0u 0:00.0s 33k] : delay sumin -1 0 (7 stages examined.) [0:00.0u 0:00.0s 34k] : critical Node ssum is driven low at 5.11ns ...through fet at (34, 180) to GND after dlatch_2/inv_0[1]/a is driven high at 4.11ns ...through fet at (22, 190) to Vdd after dlatch_2/inv_0[0]/a is driven low at 3.00ns ...through fet at (4, 190) to sumin after sumin is driven low at 0.00ns [0:00.0u 0:00.0s 34k] : clear [0:00.0u 0:00.0s 34k] : inputs ph2 -ph2 sumin [0:00.0u 0:00.0s 34k] : outputs ssum [0:00.0u 0:00.0s 34k] : set 1 ph2 Marking transistor flow... Setting Vdd to 1... Setting GND to 0... [0:00.0u 0:00.0s 34k] : set 0 -ph2 [0:00.0u 0:00.0s 34k] : delay sumin 0 -1 (4 stages examined.) [0:00.0u 0:00.0s 34k] : critical Node ssum is driven high at 7.89ns ...through fet at (34, 190) to Vdd after dlatch_2/inv_0[1]/a is driven low at 6.89ns ...through fet at (22, 180) to GND after dlatch_2/inv_0[0]/a is driven high at 5.78ns ...through fet at (10, 180) to sumin after sumin is driven high at 0.00ns [0:00.0u 0:00.0s 34k] : clear [0:00.0u 0:00.0s 34k] : inputs ADDOUT -ADDOUT sumin [0:00.0u 0:00.0s 34k] : outputs sumout [0:00.0u 0:00.0s 34k] : check Marking transistor flow... Setting Vdd to 1... Setting GND to 0... [0:00.0u 0:00.0s 34k] : set 1 ADDOUT [0:00.0u 0:00.0s 34k] : set 0 -ADDOUT [0:00.0u 0:00.0s 34k] : delay sumin -1 0 (9 stages examined.) [0:00.0u 0:00.0s 34k] : critical Node ssum is driven low at 5.11ns ...through fet at (34, 180) to GND after dlatch_2/inv_0[1]/a is driven high at 4.11ns ...through fet at (22, 190) to Vdd after dlatch_2/inv_0[0]/a is driven low at 3.00ns ...through fet at (4, 190) to sumin after sumin is driven low at 0.00ns [0:00.0u 0:00.0s 34k] : clear [0:00.0u 0:00.0s 34k] : inputs ADDOUT -ADDOUT sumin [0:00.0u 0:00.0s 34k] : outputs sumout [0:00.0u 0:00.0s 34k] : check Marking transistor flow... Setting Vdd to 1... Setting GND to 0... [0:00.0u 0:00.0s 34k] : set 1 ADDOUT [0:00.0u 0:00.0s 34k] : set 0 -ADDOUT [0:00.0u 0:00.0s 34k] : delay sumin 0 -1 (5 stages examined.) [0:00.0u 0:00.0s 34k] : critical Node ssum is driven high at 7.89ns ...through fet at (34, 190) to Vdd after dlatch_2/inv_0[1]/a is driven low at 6.89ns ...through fet at (22, 180) to GND after dlatch_2/inv_0[0]/a is driven high at 5.78ns ...through fet at (10, 180) to sumin after sumin is driven high at 0.00ns [0:00.0u 0:00.0s 34k] [0:00.0u 0:00.0s 34k] : [0:00.1u 0:00.1s 34k] Crystal done.