The following is the MEG program for the PLA which will be our state machine and heart of the controller. Note that this is more or less a ring counter (a binary counter with a decoder). The latches in the CPU are generally only enabled for one cycle or state in the machine, so many of them will simply have the signal corresponding to the desired state as their enable (it will be anded with the clock). This greatly simplifies the PLA (which is why the code is so short). Some multiplexers will also be able to draw their control directly from the PLA (if their select signal is dependent only on the state). At worst case, one or more of the state lines will have to be involved in some very relatively simple logic with other inputs to the controller (the current instruction, condition codes, etc.). Note that we do not spell out everything here, but the information here and on the logic page will be all that is necessary to figure out exactly how to generate every control signal. One important note is that the outputs are active low to simplify generation of register store signals. Since we need the AND of a clock and a state we can instead use the inverted clock NORed with the inverted state signal.
-- control.meg
INPUTS: RESTART HALT;
RESET ON RESTART TO init(if1state if2state alu1state alu2state haltstate);
init : GOTO fetch1(initstate if2state alu1state alu2state haltstate);
-- MEG file for CPU control unit
-- Chris Hughes & Corey Pie'
-- ELEC 422
-- Project
OUTPUTS: initstate if1state if2state alu1state alu2state haltstate;
fetch1 : GOTO fetch2(initstate if1state alu1state alu2state haltstate);
fetch2 : GOTO alu1(initstate if1state if2state alu2state haltstate);
alu1 : GOTO alu2(initstate if1state if2state alu1state haltstate);
alu2 : if HALT then halting(initstate if1state if2state alu1state alu2state)
else fetch1(initstate if2state alu1state alu2state haltstate);
halting : GOTO halting(initstate if1state if2state alu1state alu2state);