Inputs of this simulation: CLKA, CLKB, LDPCBUF, CLEARPC, INCPC, WRITEIM, READIM, LDIMBUFLO, LDIMBUFHI, ENIMBUFLO, ENIMBUFHI, LDIMBUFOUT, BRANCH, ADR{3:0} (the 4-bit input to the PC Unit), INLO{3:0} (the lower 4 bits input from the IN Register), and INHI{3:0} (the upper 4 bits input from the IN Register).
Main Outputs of this simulation: OUTHI{3:0}, OUTLO{3:0}
From the simulation, we see that IM works as it is supposed to. Data from ADR is stored into the PC as the address location. When LDIMBUFHI and LDIMBUFLO are asserted, the input bits INLO and INHI are stored into the INBUF. (NOTE: IN is only 4-bits long. The 4 bits of INLO and INHI arrive at different clock cycle) When WRITEIM is asserted, the data from INBUF are latched to the memory storage location specified by the PC. When ENIMBUFLO or ENIMBUFHI are asserted after READIM and LDIMBUFOUT are asserted, the stored value goes out into the bus as expected.
