Arithmetic Logic Unit (ALU)

The ALU is a four-bit structure which performs the following arithmetic and logical operations: add, addx, add immediate, subtract, and, or, not, and shift right logical. The add instruction uses the value of the TP register (read from the instruction) to index data memory and adds the value accessed in data memory to the value of the accumulator. The addx instruction performs nearly the same operation, but it uses the contents of the indexing register (IX) rather than the TP to index data memory. The add immediate instruction adds the value of the TP (read from the instruction) to the value of the accumulator. The subtract instruction uses the contents of the TP register to index data memory and subtracts the value in the accumulator from the value accessed in data memory. The and instruction performs a bit-wise and of the value in the accumulator and the contents of the TP. The or instruction performs a bit-wise or of the value in the accumulator and the contents of the TP. The not instruction performs a bit-wise not of the value in the accumulator. Finally, the shift right logical instruction shifts the value in the accumulator one bit to the right and replaces the most significant bit with a zero.

The full ALU cell, ALUFIN, is composed of several sub-sections, which are described in more detail below:

Combinational Logic

The majority of the combinational logic for the ALU is contained within the ALL cell. There are four ALL cells in the ALU--one for each bit. Each ALL cell has to data inputs: x and y. The x input is taken from the bus, while the y input comes from the via the . In its most basic form, the ALL cell is a one-bit ripple-carry adder, consisting of and, or and xor gates. In order to conserve chip space, however, the other ALU outputs are also taken from this cell. When the appropriate control signals are used, the AND, OR, and NOT values can be obtained at various locations within ripple-carry adder. The table below shows the necessary values of the ALL control signals for each output.

Internal Decoder

Many of the control signals for the ALU are generated internally by a simple decoder. Rather than obtaining control signals from the PLA, the lower three bits of the opcode for each instruction is input to a decoder (mpla) which then outputs the control signals to determine what type of operation is being performed (i.e. control of the ASC and PATH signals) and which output to propagate to the accumulator. The decoder was designed using the mpla tool, but the clocks of the resulting pla-decoder are tied to vdd (and the clock_bars tied to ground), making the decoder purely combinational. The benefits of operating an internal decoder rather than taking controls from the PLA are that it minimizes the size of the PLA and also causes fewer timing complications by removing timing constraints from the operation of the ALU control signals. The following table summarizes which 3-bit opcodes specify which ALU instructions, as well as what control signals are asserted for those instructions.

3-Bit Opcode Operation Signals Asserted
000 ADDX Assig
010 ADDI Assig
110 ADD Assig
111 SUBTRACT Assig Carry
001 AND Andsig
100 OR Orsig Carry Path
101 NOT Notsig Path
011 Shift Right Logical Srsig

Output Multiplexor

Because the results of the various alu operations are obtained from different locations within the same circuit, all operations are being performed at all times (although the results may not be correct since the control signals ASC and PATH will not be appropriate for all operations). Thus, we need a multiplexor to choose which of the result signals will be the official output of the ALU and will be passed to the accumulator. This is achieved through the use of an array of transmission gates. Each of the outputs of each ALL cell are sent to a tgate (cell JGATE), and these tgates are controlled by output signals of the internal decoder. The outputs of the tgates for all the outputs of each bit (or ALL cell) are connected, and only one tgate is enabled at any given time. Thus, depending upon the signal output by the decoder, the output for an ADD, SUBTRACT, AND, OR, NOT, or SRL is passed through the array of tgates and sent to the accumulator. Because the decoder controls both the control inputs to the ALL cells (ASC and PATH) and the control inputs to the tgate array (ANDSIG ORSIG ASSIG NOTSIG and SRSIG), we can be certain that these signals are so that the output will be correct for the given operation.

Accumulator Multiplexor

The accumulator multiplexor is simply a 4-bit, 2-input mux. It chooses whether the values on the bus or the output of the ALU will be sent to the accumulator to be stored. The accumulator multiplexor is controlled by a signal called BUS2ACC, which is generated in the main PLA. The BUS2ACC signal is inverted and connected to the signals that pass the ALU value to the accumulator. Thus, a high BUS2ACC passes the bus value to the accumulator, while a low BUS2ACC passes the ALU value to the accumulator. The accumulator multiplexor aids in the initial loading of the accumulator. The accumulator is a clearable latch, but without the accumulator multiplexor, loading a value other than zero into the accumulator would require a clear of the accumulator followed by an add immediate of the accumulator and the value to be loaded. With the accumulator multiplexor in place, the value can simply be written to the bus and loaded into the accumulator from the bus.

Accumulator

The accumulator is clearable latch that exhibits clocked loading, as well as clocking enabling. The latch (j_pclatch) is based upon pclatch, which is used in the pc, and has a very similar structure. It is composed of a control cell (j_pccontrol) and four latch bits (j_pcbit). The accumulator is clocked on clock a and receives its control inputs (LDACC, CLEARACC, and ENACC) from the main PLA. The LDACC and ENACC are "anded" with clka, but the CLEARACC signal is asynchronous, allowing the accumulator to be cleared at any time. As mentioned in the above Accumulator Multiplexor section, the accumulator can be loaded from either the bus or the output of the ALU. When the ENACC signal is asserted, the output of the accumulator is written to the bus. If ENACC is not asserted, the accumulator doesn't drive the bus, but it still holds a value and "feeds" that value back to the input of the accumulator via the Accumulator Buffer.

Accumulator Buffer

The accumulator buffer (j_buff) is a simple buffer based upon the pc_buffer cell. Like the accumulator itself, the accumulator buffer is composed of a control cell (j_control) and four buffer bits (j_latch). The input to the accumulator buffer is taken from the accumulator, and the output is the second four-bit input to the alu, y{3:0}. The load signal for the accumulator buffer (LDALUBUF), which is taken from the main PLA, is clocked on clock a, but the buffer is always enabled, and thus the y input to the ALU is always defined. When LDALUBUF is asserted, the accumulator buffer reads from the accumulator. As mentioned above, the inputs to the accumulator buffer are taken from within the accumulator, so the accumulator need not be enabled for the accumulator buffer to laod a defined value. The purpose of the accumulator buffer is to "hold" the value of the accumulator for one or more clock cycles until the PLA determines that the inputs to the ALU need to change. Without the accumulator buffer, the y input to the ALU would change before the beginning of the next clock cycle, causing a "race" of values through the ALU.