Instruction Set Architecture Table 1.1: Instruction Set Architecture

ALU

ADD	TP -> MA ACC <- ACC + DM[MA]
ADDI	ACC <- TP + ACC
ADDX	TP <- DM[IX] ACC <- TP + ACC
SUB	TP -> MA ACC <- ACC - DM[MA]
SR	ACC <- ACC >> 1
OR	ACC <- ACC \|\| TP
AND	ACC <- ACC & TP
NOT	ACC <- ACC'

DATA ACCESS

ST	TP -> MA ACC -> DM[MA]
LD	TP -> MA DM[MA] -> ACC
LDX	IX <- DM[TP]

CONTROL

BEZ If ACC == 0
Then PC <- PC + TP

OTHER

NOP No operation

HLT PC doesn't increment

WO OUT <- ACC

RIP PC <- 0
Wait for user input