Maximum Clock Frequency Determination

As discussed in the other sub-sections of the Performance Analysis section, both Crystal and spice were used to find the longest path through the circuit. Because of the high concentration of combinational logic, it was assumed that the ALU would provide the longest path. Both Crystal and spice determined that the longest path through the ALU is from the least significant bit of the input to the alu from the bus, x(0), to the most significant bit of the accumulator, b(3). However, Crystal estimated the path to be approximately 265 ns, while the spice model gave an estimated tim of only 40 ns. Because the spice model takes more physical parameters into account when calculating the longest path, it is generally more accurate (and definitely less conservative) than the Crystal model. Thus, we have chosen to use the spice model to estimate the maximum clock frequency of our chip.

The signals driving the bus are Valid B--Stable A signals, and are thus first asserted very soon after the rise of clock B. The accumulator is stores data on clock A, so the output of the alu must reach it before clock A falls. Thus, the longest path through the circuit covers the clock B pulse, the space between the clock B and clock A pulses, and the clock A pulse, which is equal to 3/4 of a complete clock cycle.

Computing a rigorous maximum clock frequency, we would first determine that the minimum clock period is equal to 4/3 * 40 ns, which is approximately equal to 55 ns. Inverting this period gives us a maximum clock frequency of approximately 18.2 MHz. As with any engineering design, however, we want to allow a margin of error in which the performance of the circuit can fluctuate. Thus, to give a more conservative estimate, we will double the minimum clock period, resulting in 110 ns. This value gives a maximum clock frequency of 9 MHz.

The Maximum Clock Frequency = 9 MHz