Test for IM seg fault
Expected Behavior:
On BNEZ, ACC is not zero, so Branch
But, the target address is 12, so IMSEG
CHIPMONC ASSEMBLY
addi 0101
bnez 1100
CMD FILE
| branch to 13 for IMSEG
clock p_clka 0 1 0 0
clock p_clkb 0 0 0 1
vector in p_in{3:0}
vector out p_out{3:0}
vector state p_sb{0:3}
vector PC p_pc{3:0}
vector IR p_ir{3:0}
vector bus p_bus{3:1}
ana in p_enter out p_restart state PC IR p_clka p_clkb p_zeroflag p_carryout p_dmseg p_imseg p_loading p_branch p_halted bus
V p_RESTART 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V in 0000 0000 0000 1010 0101 1111 1111 0011 1100 1111 1111 0000 0000 1111 1111 0011 0001 1111 1111 1111 0111 1111 1111 0011 0010 1111 1111 0000 0000 1111 1111 0010 0000 1111 1111 1100 1010 1111 1111 0010 0000 1111 1111
V p_enter 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
R
SIMULATION
Notice:
PLA goes to Fault state after 2nd instruction