Test for DMSEG<BR>
Should fault on 2nd instruction<BR>
<BR>
<BR>
<hr>
CHIPMONC ASSEMBLY<BR>
<BR>
addi 1111<BR>
st 1000<BR>
addi 0000<BR>
halt<BR>
<BR>
<hr>
CMD FILE<BR>
<BR>
<BR>
|dmseg on store<BR>
<BR>
clock p_clka 0 1 0 0<BR>
clock p_clkb 0 0 0 1<BR>
<BR>
vector in p_in{3:0}<BR>
vector out p_out{3:0}<BR>
vector state p_sb{0:3}<BR>
vector PC p_pc{3:0}<BR>
vector IR p_ir{3:0}<BR>
vector bus p_bus{3:1}<BR>
<BR>
ana in p_enter out p_restart state PC IR p_clka p_clkb p_zeroflag p_carryout p_dmseg p_imseg p_loading p_branch p_halted bus<BR>
<BR>
V p_restart	1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <BR>

<BR>
<BR>
V in	0000 0000 0000 1010 1111 1111 1111 0101 1000 1111 1111 1010 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111<BR>
<BR>
V p_enter		0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <BR>
<BR>
R
<BR>

<hr>
<img src="pic/f3.gif"><br>
<h3>Notice:
<li>The 2nd instruction is a load to location 1000
<li>The PLA goes to a Fault state after that instruction