PSEUDO CODE
vector a = {4, 7};
b=0;
for (i=0; i< 2; i++)
b+=a[i];
print(b);
---------------------------
MONC ASSEMBLY
;; First store the data
addi 4 Acc=4
st 0 store 4 to DM[0]
addi 3 Acc=7
st 1 store 7 to DM[1]
;; Set up the loop bounds ('i' in the C code)
;i counter
and 0
st 7 store 0 to DM[7]
;clear destination (sumsofar)
st 5
;size
addi 2 acc=2
st 6 store 2 to DM[6]
rip
;; Start exectuting the loop
loop:
ld 5 acc=sumsofar
ldx 7 ix=Aaddress
addx acc=mem[ix]+sumsofar
st 5 mem[5]=sumsofar
ld 7 acc=i
addi 1 acc++
sub 6 acc=mem[6]-acc; acc=size-(i+1)
st 7 mem[7]=i+1
bnez loop
rip
;; print the results
ld 5
wo
;;finished
halt
MONC MACHINE
;initial block
1010 0100
0101 0000
1010 0011
0101 0001
1001 0000
0101 0111
0101 0101
1010 0010
0101 0110
0001 0000
;loop block
0100 0101
0111 0111
1000 0000
0101 0101
0100 0111
1010 0001
1111 0110
0101 0111
0011 1000
0001 0000
;once loading signal become high
0100 0101
0010 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
CMD FILE
| store vector then add values
| output 1011
clock p_clka 0 1 0 0
clock p_clkb 0 0 0 1
vector in p_in{3:0}
vector out p_out{3:0}
vector state p_sb{0:3}
vector PC p_pc{3:0}
vector IR p_ir{3:0}
vector bus p_bus{3:1}
ana in p_enter out p_restart state PC IR p_clka p_clkb p_zeroflag p_carryout p_dmseg p_imseg p_loading p_restart p_enter p_branch p_halted bus
|enter init block
V p_RESTART 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V in 0000 0000 0000 1010 0100 1111 1111 0101 0000 1111 1111 1010 0011 1111 1111 0101 0001 1111 1111 1001 0000 1111 1111 0101 0111 1111 1111 0101 0101 1111 1111 1010 0010 1111 1111 0101 0110 1111 1111 0001 0000 1111 1111
V p_enter 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
R
|run init block
V
V p_RESTART 0
V p_enter 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
|enter loop block
V
V in 0000 0000 0000 0100 0101 1111 1111 0111 0111 1111 1111 1000 0000 1111 1111 0101 0101 1111 1111 0100 0111 1111 1111 1010 0001 1111 1111 1111 0110 1111 1111 0101 0111 1111 1111 0011 1000 1111 1111 0001 0000 1111 1111
V p_enter 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
R
|run loop block
V
V p_enter 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V p_START 0
R
|enter print block after loop is done
V
V in 0000 0000 0000 0100 0101 1111 1111 0010 0000 1111 1111 0000 0000 1111 1111 0101 0101 1111 1111 0100 0111 1111 1111 0101 0001 1111 1111 1110 0101 1111 1111 0101 0111 1111 1111 0011 0000 1111 1111 0001 0000 1111 1111
V p_enter 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
R
|run it
V
V p_RESTART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V p_enter 0
R
SIMULATION
Notice
Alot of stuff happens
We get the correct output in the end...