Test12: Simple ALU instructions Command File, Result

Command File

clock clka 0 1 0 0
clock clkabar 1 0 1 1
clock clkb 0 0 0 1
clock clkbbar 1 1 1 0
vector ir ir3 ir2 ir1 ir0
vector state s1 s2 s3 s4

ana state entp ldacc bus2acc loading ir

V RESTART 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

V LOADDONE 1

V ENTER 1

V DMSEG 0

V IMSEG 0

V ir 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1010 1010 1010 1010 1010 1011 1011 1011 1011 1011 1100 1100 1100 1100 1100 1101 1101 1101 1101 1101

R

Notice:

• The opcodes correspond to AND, ADDI, SR, OR, and NOT
• During EX the ACC is loaded with the result of the ALU operation, so BUS2ACC is low while LDACC
• Instructions requiring two operands (ADDI, AND) need the value in the TP so ENTP is asserted