Test4: HALT instruction

Command File, Result

Command File

| HALT instruction

clock clka 0 1 0 0
clock clkabar 1 0 1 1
clock clkb 0 0 0 1
clock clkbbar 1 1 1 0
vector ir ir3 ir2 ir1 ir0
vector state s1 s2 s3 s4

ana state loading ir

V RESTART 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

V LOADDONE 1

V ENTER 1

V ir 0110

V DMSEG 0

V IMSEG 0

V ir 0000

R


Simulation


Notice: