Test8: LD instruction Command File, Result

Command File

clock clka 0 1 0 0
clock clkabar 1 0 1 1
clock clkb 0 0 0 1
clock clkbbar 1 1 1 0
vector ir ir3 ir2 ir1 ir0
vector state s1 s2 s3 s4

ana state entp ldma readdm ldtp ldacc bus2acc loading ir

V RESTART 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

V LOADDONE 1

V ENTER 1

V DMSEG 0

V IMSEG 0

V ir 0100

R

Notice:

• During ID, the MA is loaded with the address location in the TP (ENTP and LDMA)
• During EX, the data in DM is loaded into the ACC (READDM, LDACC, and BUS2ACC)
• BUS2ACC triggers the ALU mux to pass the bus, rather than the ALU result, to the ACC