Test2: Control Signals in Loading Mode Command File, Result

Command File

clock clka 0 1 0 0
clock clkabar 1 0 1 1
clock clkb 0 0 0 1
clock clkbbar 1 1 1 0

vector state s1 s2 s3 s4

ana state enin ldimbuflo ldimbufhi writeim incpc loading ldpcbuf

V RESTART 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

V LOADDONE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

V ENTER 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0

V DMSEG 0
V IMSEG 0
R

Notice:

• ENIN is high for two cycles, to pass the opcode and then the operand
• While ENIN is high, LDIMBUFLO goes high to store the opcode to the low bits of the IM buffer
• While ENIN is high, LDIMBUFHI goes high to store the operand to the high bits of the IM buffer
• After the 8 bits of the buffer have been loaded, WRITEIM goes high to store the instruction to memory
• Finally, INCPC stores the next instruction address to the PC register
• At least one cycle before INCPC, LDPCBUF loads the buffer with the current PC value to calculate the next PC address