States
There are basically two loops in normal PLA execution. The first is used
to load instructions into data memory. The second executes those
instructions.
Loading Mode
Due to pin limitations, we could
not read all 8 bits of an instruction at once. Therefore, two passes are
used: first the opcode is loaded into the lower bits of a buffer
register, then the 4-bit opcode is stored to the upper bits of this
register. In the next cycle, this entire instruction is copied into an
8-bit memory location. Finally, the Program Counter (PC) is incremented to
indicate where the next instruction will be stored. Then the PLA returns
to a WAIT state until the next opcode is ready; when the user has the
desired bits at the input pads, she asserts the ENTER signal to trigger the
PLA.
Execution Mode
The PC asserts a flag when its value is 10012, indicating that
10 instructions have been loaded and causing the PLA to move into its
instruction-execution loop. In EXECUTION mode, 4 stages are repeated:
Instruction Fetch, Instruction Decode, Operand Fetch, and Execution.
IF takes three cycles, first to put the desired instruction into a buffer
register, the to move the low bits of that into the IR, which holds the
opcode, and finally, the upper 4-bit operand is moved into the TP
register. ID determines if the instruction requires a memory access, in
which case the address of the data must be moved to the MA to address Data
Memory. Otherwise, the instruction moves directly into the execution
stage. If it is an ALU instruction that requires and operand from memory,
the operand is fetched using the address that was loaded into the MA in the
previous stage. Finally, all the preliminary work has been done, the
instruction is Executed.
The instruction execution loop continues until a RIP instruction is
decoded, signifying that new instructions are to be loaded into the IM,
returning the PLA to Loading Mode.
Other States
A HALT instruction indicates program completion and sends the PLA to a Halt
state.
The only other ways to break out of the loops are due to errors.
Segmentation Faults can occur either on IM or DM accesses. If an
instruction branches to an invalid address, or there is no RIP or HALT at
the end of an instruction block, the PLA will attempt to fetch an
instruction from a memory location that does not exist. Additionally, an
error could occur if an operand is attempted to be fetched from a
non-existent data location. Note that all of these errors are due to
problems in the software.
There could potentially be a problem loading more than ten instructions,
but should not occur if the hardware is functioning correctly.
Once in a Fault or Halted state, the PLA must be restarted.
