Simulation
Notice:
- States 0-4 are repeated 3 times, as 3 instructions are loaded
- States 1 and 2 must wait for the external ENTER signal
- When LOADDONE goes high, the PLA exits Loading Mode
- States 6-12 are repeated in Exectution Mode.
clock clka 0 1 0 0
clock clkabar 1 0 1 1
clock clkb 0 0 0 1
clock clkbbar 1 1 1 0
vector ir ir3 ir2 ir1 ir0
vector state s1 s2 s3 s4
ana state enter loaddone loading ir
V RESTART 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V LOADDONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
V ENTER 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
V DMSEG 0
V IMSEG 0
V IR3 0
V IR2 1
V IR1 1
V IR0 0
R