JAWs State Machine

09 December 1998

10 December 1998
Added RegRead to second state of LW instruction.

09 December 1998

Removed Mem2Reg from WB stage of ADDI, SLL, ADD, SUB, NOT, AND, OR.

17 November 1998

NOOP added.

WriteBack stage of ADDI changed to include ImpReg3 signal.

15 November 1998

Mem2Reg added to WB of LW

SetPC=1 added to the second bubble for each instruction

Start(ClearRegs=1) added, going to IF.

06 November 1998

Only IF state at top. Created three well-defined states: IF, RegRead/ALUexec, and WriteBack.

Register reads are performed in the second of these three states. ZERO and LDI have no register reads (only writes), so they take place in the third state.

11 October 1998

Start state changed to Instruction Fetch state and RegAccess state.

06 October 1998

Original submitted.