ID: 59673
P-NAME: bob
Fab-ID: T01SCZ
P-P: 
REPORT:

Our chip is an ALU which performs 2's compliment addition, subtraction and
multiplication as well as unsigned division.  The chip implements a single
adder to perform these operations.  Multiplication uses a shift and add
algorithm which uses the least significant bit of the first input as a
control signal to decide between adding the multiplicand or zero to the
accumulated product.  This input is then shifted through eight total cycles.
The final cycle either adds or subtracts depending on the sign.  Division
uses a subtract and shif algorithm which uses the most significant bit of
the subtraction as a comparison to decide whether or not to replace the
original input value.  The chip is to output the complete sum or difference
with appropriate carry.  In the case of multiplication it outputs the two
halves of the product on subsequent clock cycles.  In the case of division
it outputs the remainder and then the integer result.  In all cases the
final output is held until a new result from the next calculation is
determined. 

We had no operational chips due to an undetected error in our design.  Our 
chip simulated correctly using Irsim so we were very surprised to find that 
the chip only outputs zeros.  There are several possible reasons for our 
failure including Irsim connecting signals of the same name without alerting
us that the wires were not connected.  The implicit connection without
warning caused a failure in one other group in our class.  We also may have 
caused an error in the chip by not enabling all of the pads, even the ones 
that had no connected signal.  Un-enabled pads may cause oscillation in the 
pad frame, causing other signals to have too much noise.  We only witnessed 
a sympathetic oscillation on one pad; when an input signal went high, the 
pad next to it showed a small version of the same signal.  The pad error may
have caused enough attenuation and noise to disable the circuit.  One final
reason could be missing substrate contacts on some of our buffer circuits.  
The contacts are not essential, but they significantly improve the behavior 
of the transistor.

We were unable to complete any speed tests due to our chips not functioning.

The packages all arrived undamaged due to shipping.

URL: www.owlnet.rice.edu/~ablair/GroupB

SUBMITTED BY: 
Adam Blair (ablair@rice.edu)
Joe Shifflett (jwshiffl@rice.edu)

REQUEST: END