Group D: Radix-8 Fast Multiplication
Group members
Functional description
I/O pin map
Algorithm explanation
Algorithm implementation notes
User interface
Circuit design
Hardware block diagram with timing labels
Chart of signal values and timing labels
Irsim results of subcells
Irsim results of entire chip
PLA description
State tranisition diagram
Input to meg
Irsim simulation results
Spice simulation results
Circuit layout
Plots of low-level cells
Cell heirarchy
Floor plan
Full plot of chip
Performance ananysis
Crystal analysis of longest path
Spice analysis of critical sub-circuit
Summary
References
Division of work by group members
Mechanism for generating data files
Testing
Photograph of chip
Testing methods and results
Mosis report