The critical path is the output from the Lower 4 latch, which goes through the FESZ controller, whose outputs go into the FESZ, which in turn is the longest-delayed input into the adder. I never could simulate the FESZ in Spice because of a strange syntax error, but the delay in the FESZ bitslice is about 5ns. The delay of the FESZ controller is another 5ns. Eric determined that the longest path through the adder was 16ns, so allowing a little for routing and multiplexers, the longest path from one half clock cycle to the next is about 27ns, which would make our maximum clock frequency about 37MHz.

FESZ controller Spice results:

FESZ bitslice

12-bit adder