Radix-8 multiplication is an extention of the more widely used Radix-4 multiplication (also known as Booth recoding). For the added hardware and complexity, it is considerably faster than Radix-4 due to a reduction in the number of iterations used to implement the algorithm. It has been shown to be cost effective in many scenarios, with a greater jump in performance between Radix-4 and Radix-8 than would be appreciated by going to the next level (Radix-8 to Radix-16).
Our chip is designed to optomize this algorithm, using two nine-bit inputs rather than the more traditional eight-bits. Therefore, our chip must satisfy an eighteen-bit output.
Additions within the multiply algorithm are to carried out by a carry-skip adder, that is a half-way implementation between a carry-look-ahead adder and a ripple-carry adder. This implementation exemplifies the tradeoffs between the speed of a carry-look-ahead with the compact and ease of a ripple-carry, since it will occupy less chip space than a true carry-look-ahead, but be considerably faster than a ripple-carry. Since our chip calls for a twelve-bit adder, we have decided to break up the addition into three four-bit blocks.