Each box in the chart contains both a value (may be generic) and a Karplus timing parameter for the particular signal at the particular time, unless an x appears, in which case both the value and timing parameter are unknown. The data shown for the latches is for the contents of that latch, as distinct from the control signals from the PLA used to control that latch, which may themselves be delayed by an intermediary temporary latch, not shown.

	Time	Inputs		Control signals												Latches
cycle	start	ready	data input	PLA state	loadAtemp	loadB	load3B	Asource	addSource	loadPL	resetP	loadL	loadSlave	loadtemp	finish	A	B	3B	P	A	L	P slave	A slave	lower 4
before	0 V	x	x	idle S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	1 S	x	x	x	previous S	previous S	x	x	x	x
A1	1 V	x	x	idle S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	1 S	x	x	x	previous S	previous S	x	x	x	x
B1	x	x	x	toloadA V	0 S	0 S	0 S	x	x	0 S	1 V	0 S	0 S	0 S	0 V	x	x	x	previous S	previous S	x	x	x	x
A2	x	x	x	toloadA S	0 S	0 S	0 S	x	x	0 S	1 S	0 S	0 S	0 S	0 S	x	x	x	0 V	previous S	0 V	x	x	x
B2	x	x	x	loadedA V	1 V	0 S	0 S	0 V	x	1 V	0 V	0 S	0 S	0 S	0 S	x	x	x	0 S	previous S	0 S	x	x	x
A3	x	0 V	A V	loadedA S	1 S	0 S	0 S	0 S	x	1 S	0 S	0 S	0 S	0 S	0 S	A V	x	x	0 S	previous S	0 S	x	x	x
B3	x	x	x	loadedA S	0 V	0 S	0 S	x	x	0 V	0 S	0 S	0 S	0 S	0 S	A S	x	x	0 S	A V	0 S	x	x	x
A4	x	0 V	x	loadedA S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	0 S	A S	x	x	0 S	A S	0 S	x	x	x
B4	x	x	x	loadedA S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	0 S	A S	x	x	0 S	A S	0 S	x	x	x
A5	x	0 V	x	loadedA S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	0 S	A S	x	x	0 S	A S	0 S	x	x	x
B5	x	x	x	loadedA S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	0 S	A S	x	x	0 S	A S	0 S	x	x	x
A6	x	1 V	x	loadedA S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	0 S	A S	x	x	0 S	A S	0 S	x	x	x
B6	x	x	x	computing3B V	0 S	1 V	0 S	x	0 V	0 S	0 S	1 V	0 S	0 S	0 S	A S	x	x	0 S	A S	0 S	x	x	x
A7	x	x	B V	computing3B S	0 S	1 S	0 S	x	0 S	0 S	0 S	1 S	0 S	0 S	0 S	A S	B V	x	0 S	A S	0 S	x	x	x
B7	x	x	x	compute1 V	0 S	0 V	1 V	x	x	0 S	0 S	0 V	0 S	0 S	0 S	A S	B S	x	n V	A S	0 S	x	x	x
A8	x	x	x	compute1 S	0 S	0 S	1 S	x	x	0 S	0 S	0 S	0 S	0 S	0 S	A S	B S	3B V	n S	A S	0 S	x	x	x
B8	x	x	x	compute2 V	0 S	0 S	0 V	1 V	1 V	1 V	0 S	1 V	1 V	1 V	0 S	A S	B S	3B S	n S	A S	0 S	x	x	x
A9	x	x	x	compute2 S	0 S	0 S	0 S	1 S	1 S	1 S	0 S	1 S	1 S	1 S	0 S	A S	B S	3B S	n S	A S	0 S	n V	n V	n V
B9	x	x	x	compute3 V	0 S	0 S	0 S	1 S	1 S	1 S	0 S	1 S	1 S	1 S	0 S	A S	B S	3B S	n V	n V	n V	n S	n S	n S
A10	x	x	x	compute3 S	0 S	0 S	0 S	1 S	1 S	1 S	0 S	1 S	1 S	1 S	0 S	A S	B S	3B S	n S	n S	n S	n V	n V	n V
B10	x	x	x	idle V	0 S	0 S	0 S	1 S	1 S	1 S	0 S	1 S	1 S	1 S	0 S	A S	B S	3B S	n V	n V	n V	n S	n S	n S
A11	0 V	x	x	idle S	0 S	0 S	0 S	1 S	1 S	1 S	0 S	1 S	1 S	1 S	0 S	A S	B S	3B S	n S	n S	n S	n V	n V	n V
B11	x	x	x	idle S	0 S	0 S	0 S	x	x	0 V	0 S	0 V	0 V	0 V	1 V	A S	B S	3B S	n V	n V	n V	n S	n S	n S
A12	0 V	x	x	idle S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	1 S	A S	B S	3B S	n S	n S	n S	n S	n S	n S
B12	x	x	x	idle S	0 S	0 S	0 S	x	x	0 S	0 S	0 S	0 S	0 S	1 S	A S	B S	3B S	n S	n S	n S	n S	n S	n S